From 8e2ba718d0430e74a4f2f9fdb8b48bfddd7ef193 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 10:16:48 -0600 Subject: [PATCH] [Doc] update documentation on the new option '--testbench_type' --- .../openfpga_commands/fpga_verilog_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c41887484..a1303941d 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -173,6 +173,10 @@ write_simulation_task_info Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + .. option:: --testbench_type + + Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``. + .. option:: --verbose Show verbose log