[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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tangxifan
parent
5075c68418
commit
8db19c7af9
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@ -122,7 +122,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
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/********************************************************************
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* A wrapper function to call the full testbench generator of FPGA-Verilog
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*******************************************************************/
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int write_full_testbench(OpenfpgaContext& openfpga_ctx,
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int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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@ -170,5 +170,45 @@ int write_full_testbench(OpenfpgaContext& openfpga_ctx,
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options);
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}
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/********************************************************************
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* A wrapper function to call the preconfigured wrapper generator of FPGA-Verilog
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*******************************************************************/
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int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_print_formal_verification_top_netlist(true);
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/* If pin constraints are enabled by command options, read the file */
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PinConstraints pin_constraints;
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if (true == cmd_context.option_enable(cmd, opt_pcf)) {
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pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
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}
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return fpga_verilog_preconfigured_fabric_wrapper(openfpga_ctx.module_graph(),
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openfpga_ctx.bitstream_manager(),
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g_vpr_ctx.atom(),
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g_vpr_ctx.placement(),
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pin_constraints,
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openfpga_ctx.io_location_map(),
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openfpga_ctx.fabric_global_port_info(),
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openfpga_ctx.vpr_netlist_annotation(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol,
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options);
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}
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} /* end namespace openfpga */
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@ -21,7 +21,10 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
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int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_full_testbench(OpenfpgaContext& openfpga_ctx,
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int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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} /* end namespace openfpga */
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@ -123,9 +123,9 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
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}
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/********************************************************************
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* - Add a command to Shell environment: write full testbench
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* - Add associated options
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* - Add command dependency
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* - add a command to shell environment: write full testbench
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* - add associated options
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* - add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
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@ -133,46 +133,88 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_full_testbench");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for HDL netlists");
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/* add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--bitstream'*/
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CommandOptionId bitstream_opt = shell_cmd.add_option("bitstream", true, "Specify the bitstream to be loaded in the testbench");
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/* add an option '--bitstream'*/
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CommandOptionId bitstream_opt = shell_cmd.add_option("bitstream", true, "specify the bitstream to be loaded in the testbench");
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shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING);
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/* Add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "Specify the file path to the fabric HDL netlist");
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* Add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "Specify the file path to the pin constraints");
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/* add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* Add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
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/* add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "specify the file path to the reference verilog netlist");
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shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
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/* Add an option '--fast_configuration' */
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shell_cmd.add_option("fast_configuration", false, "Reduce the period of configuration by skip certain data points");
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/* add an option '--fast_configuration' */
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shell_cmd.add_option("fast_configuration", false, "reduce the period of configuration by skip certain data points");
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists");
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/* Add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "Initialize all the signals in Verilog testbenches");
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/* add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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/* Add command to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate full testbenches for an FPGA fabric");
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/* add command to the shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate full testbenches for an fpga fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_full_testbench);
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/* Add command dependency to the Shell */
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/* add command dependency to the shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - add a command to shell environment: write preconfigured fabric wrapper
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* - add associated options
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* - add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_preconfigured_fabric_wrapper");
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/* add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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/* add command to the shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate a wrapper for a pre-configured fpga fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_preconfigured_fabric_wrapper);
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/* add command dependency to the shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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@ -214,6 +256,17 @@ void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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add_openfpga_write_full_testbench_command(shell,
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openfpga_verilog_cmd_class,
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full_testbench_dependent_cmds);
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/********************************
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* Command 'write_preconfigured_fabric_wrapper'
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*/
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/* The command 'write_preconfigured_fabric_wrapper' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> preconfig_wrapper_dependent_cmds;
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preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_preconfigured_fabric_wrapper_command(shell,
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openfpga_verilog_cmd_class,
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preconfig_wrapper_dependent_cmds);
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}
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} /* end namespace openfpga */
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@ -313,4 +313,49 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
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return status;
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}
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/********************************************************************
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* A top-level function of FPGA-Verilog which focuses on full testbench generation
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* This function will generate
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* - A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark
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********************************************************************/
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int fpga_verilog_preconfigured_fabric_wrapper(const ModuleManager &module_manager,
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const BitstreamManager &bitstream_manager,
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const AtomContext &atom_ctx,
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const PlacementContext &place_ctx,
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const PinConstraints& pin_constraints,
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const IoLocationMap &io_location_map,
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const FabricGlobalPortInfo &fabric_global_port_info,
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const VprNetlistAnnotation &netlist_annotation,
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const CircuitLibrary &circuit_lib,
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const ConfigProtocol &config_protocol,
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const VerilogTestbenchOption &options) {
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vtr::ScopedStartFinishTimer timer("Write a wrapper module for a preconfigured FPGA fabric\n");
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std::string src_dir_path = format_dir_path(options.output_directory());
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std::string netlist_name = atom_ctx.nlist.netlist_name();
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int status = CMD_EXEC_SUCCESS;
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/* Create directories */
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create_directory(src_dir_path);
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/* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
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std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX);
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status = print_verilog_preconfig_top_module(module_manager, bitstream_manager,
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config_protocol,
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circuit_lib, fabric_global_port_info,
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atom_ctx, place_ctx,
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pin_constraints,
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io_location_map,
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netlist_annotation,
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netlist_name,
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formal_verification_top_netlist_file_path,
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options.explicit_port_mapping());
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return status;
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}
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} /* end namespace openfpga */
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@ -72,6 +72,19 @@ int fpga_verilog_full_testbench(const ModuleManager& module_manager,
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const ConfigProtocol& config_protocol,
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const VerilogTestbenchOption& options);
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int fpga_verilog_preconfigured_fabric_wrapper(const ModuleManager &module_manager,
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const BitstreamManager &bitstream_manager,
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const AtomContext &atom_ctx,
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const PlacementContext &place_ctx,
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const PinConstraints& pin_constraints,
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const IoLocationMap &io_location_map,
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const FabricGlobalPortInfo &fabric_global_port_info,
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const VprNetlistAnnotation &netlist_annotation,
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const CircuitLibrary &circuit_lib,
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const ConfigProtocol &config_protocol,
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const VerilogTestbenchOption &options);
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} /* end namespace openfpga */
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#endif
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