riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Add clock ports to the white list when adding postfix

This commit is contained in:
tangxifan 2022-02-14 11:09:00 -08:00
parent 5794561f7b
commit 8d48492ec0
5 changed files with 29 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -124,8 +124,10 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
std::string(BENCHMARK_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
@ -162,8 +164,10 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::string(FPGA_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(FPGA_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);

1
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -496,6 +496,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
std::string(),
std::string(),
prefix_to_remove,
std::vector<std::string>(),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Assign the SRAM model applied to the FPGA fabric */

18
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -78,8 +78,10 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
@ -122,7 +124,12 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
fp << "~";
}
fp << block_name;
/* For clock ports, skip postfix */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
fp << block_name;
} else {
fp << block_name << input_port_postfix;
}
if (true == use_explicit_port_map) {
fp << ")";
}
@ -174,6 +181,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value) {
/* Validate the file stream */
valid_file_stream(fp);
@ -277,14 +285,18 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
}
}
/* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1
* In addition, the input and output ports may have different postfix in naming
* due to verification context! Here, we give full customization on naming
*/
BasicPort benchmark_io_port;
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix));
/* If the port is a clock, do not add a postfix */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
benchmark_io_port.set_name(block_name);
} else {
benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix));
}
benchmark_io_port.set_width(1);
print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);

3
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -35,8 +35,10 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
@ -53,6 +55,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value);
void print_verilog_timeout_and_vcd(std::fstream& fp,

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -928,6 +928,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -945,8 +946,10 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
std::string(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
clock_port_names,
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
@ -2052,9 +2055,10 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::vector<std::string>(),
clock_port_names,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Instanciate input benchmark */
@ -2064,6 +2068,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
atom_ctx,
netlist_annotation,
pin_constraints,
clock_port_names,
explicit_port_mapping);
}