riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

simplify include_netlist.v

This commit is contained in:
tangxifan 2020-05-09 19:01:41 -06:00
parent 05d276097e
commit 8d2360a710
5 changed files with 10 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
openfpga/src/base/openfpga_verilog.cpp
View File

@ -83,8 +83,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini)); options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
fpga_verilog_testbench(openfpga_ctx.verilog_netlists(), fpga_verilog_testbench(openfpga_ctx.module_graph(),
openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(), openfpga_ctx.bitstream_manager(),
openfpga_ctx.fabric_bitstream(), openfpga_ctx.fabric_bitstream(),
g_vpr_ctx.atom(), g_vpr_ctx.atom(),

9
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -144,8 +144,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
* This testbench is created for quick verification and formal verification purpose. * This testbench is created for quick verification and formal verification purpose.
* - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated * - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
********************************************************************/ ********************************************************************/
void fpga_verilog_testbench(const NetlistManager& netlist_manager, void fpga_verilog_testbench(const ModuleManager& module_manager,
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager, const BitstreamManager& bitstream_manager,
const std::vector<ConfigBitId>& fabric_bitstream, const std::vector<ConfigBitId>& fabric_bitstream,
const AtomContext& atom_ctx, const AtomContext& atom_ctx,
@ -227,11 +226,9 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
} }
/* Generate a Verilog file including all the netlists that have been generated */ /* Generate a Verilog file including all the netlists that have been generated */
print_include_netlists(netlist_manager, print_include_netlists(src_dir_path,
src_dir_path,
netlist_name, netlist_name,
options.reference_benchmark_file_path(), options.reference_benchmark_file_path());
circuit_lib);
} }

3
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -37,8 +37,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb, const DeviceRRGSB& device_rr_gsb,
const FabricVerilogOption& options); const FabricVerilogOption& options);
void fpga_verilog_testbench(const NetlistManager& netlist_manager, void fpga_verilog_testbench(const ModuleManager& module_manager,
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager, const BitstreamManager& bitstream_manager,
const std::vector<ConfigBitId>& fabric_bitstream, const std::vector<ConfigBitId>& fabric_bitstream,
const AtomContext& atom_ctx, const AtomContext& atom_ctx,

41
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -94,11 +94,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
* that have been generated and user-defined. * that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags * Some netlists are open to compile under specific preprocessing flags
*******************************************************************/ *******************************************************************/
void print_include_netlists(const NetlistManager& netlist_manager, void print_include_netlists(const std::string& src_dir,
const std::string& src_dir,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& reference_benchmark_file, const std::string& reference_benchmark_file) {
const CircuitLibrary& circuit_lib) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX); std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */ /* Create the file stream */
@ -112,46 +110,13 @@ void print_include_netlists(const NetlistManager& netlist_manager,
print_verilog_file_header(fp, std::string("Netlist Summary")); print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */ /* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
fp << std::endl;
print_verilog_comment(fp, std::string("------ Include simulation defines -----")); print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)); print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
fp << std::endl; fp << std::endl;
/* Include all the user-defined netlists */
print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
print_verilog_include_netlist(fp, user_defined_netlist);
}
/* Include all the primitive modules */
print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include all the CLB, heterogeneous block modules */
print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include all the routing architecture modules */
print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include FPGA top module */ /* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) { print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME));
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl; fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */ /* Include reference benchmark netlist only when auto-check flag is enabled */

6
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -21,11 +21,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir, const std::string& src_dir,
const CircuitLibrary& circuit_lib); const CircuitLibrary& circuit_lib);
void print_include_netlists(const NetlistManager& netlist_manager, void print_include_netlists(const std::string& src_dir,
const std::string& src_dir,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& reference_benchmark_file, const std::string& reference_benchmark_file);
const CircuitLibrary& circuit_lib);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts); const FabricVerilogOption& fabric_verilog_opts);