diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 9a877c9f2..1d47055df 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -83,8 +83,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   
-  fpga_verilog_testbench(openfpga_ctx.verilog_netlists(),
-                         openfpga_ctx.module_graph(),
+  fpga_verilog_testbench(openfpga_ctx.module_graph(),
                          openfpga_ctx.bitstream_manager(),
                          openfpga_ctx.fabric_bitstream(),
                          g_vpr_ctx.atom(),
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 2c2ea4e93..7f82507f5 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -144,8 +144,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
  *    This testbench is created for quick verification and formal verification purpose.
  *  - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-void fpga_verilog_testbench(const NetlistManager& netlist_manager,
-                            const ModuleManager& module_manager,
+void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
@@ -227,11 +226,9 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
   }
 
   /* Generate a Verilog file including all the netlists that have been generated */
-  print_include_netlists(netlist_manager,
-                         src_dir_path,
+  print_include_netlists(src_dir_path,
                          netlist_name,
-                         options.reference_benchmark_file_path(),
-                         circuit_lib);
+                         options.reference_benchmark_file_path());
 
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index c9d194dff..301e68b3e 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -37,8 +37,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options);
 
-void fpga_verilog_testbench(const NetlistManager& netlist_manager,
-                            const ModuleManager& module_manager,
+void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index b69868d17..65e0d1ca2 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -94,11 +94,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
  * that have been generated and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
-void print_include_netlists(const NetlistManager& netlist_manager,
-                            const std::string& src_dir,
+void print_include_netlists(const std::string& src_dir,
                             const std::string& circuit_name,
-                            const std::string& reference_benchmark_file,
-                            const CircuitLibrary& circuit_lib) {
+                            const std::string& reference_benchmark_file) {
   std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
 
   /* Create the file stream */
@@ -112,46 +110,13 @@ void print_include_netlists(const NetlistManager& netlist_manager,
   print_verilog_file_header(fp, std::string("Netlist Summary")); 
 
   /* Print preprocessing flags */
-  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
-  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
-  fp << std::endl;
-
   print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
   print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
   fp << std::endl;
 
-  /* Include all the user-defined netlists */
-  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
-  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
-    print_verilog_include_netlist(fp, user_defined_netlist);
-  }
-
-  /* Include all the primitive modules */
-  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
-  /* Include all the CLB, heterogeneous block modules */
-  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
-  /* Include all the routing architecture modules */
-  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
   /* Include FPGA top module */
   print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
+  print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME));
   fp << std::endl;
 
   /* Include reference benchmark netlist only when auto-check flag is enabled */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index 52292881a..57f04032f 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -21,11 +21,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
                                   const std::string& src_dir,
                                   const CircuitLibrary& circuit_lib);
 
-void print_include_netlists(const NetlistManager& netlist_manager,
-                            const std::string& src_dir,
+void print_include_netlists(const std::string& src_dir,
                             const std::string& circuit_name,
-                            const std::string& reference_benchmark_file,
-                            const CircuitLibrary& circuit_lib);
+                            const std::string& reference_benchmark_file);
 
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
                                                const FabricVerilogOption& fabric_verilog_opts);