diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
new file mode 100644
index 000000000..f075e8781
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
@@ -0,0 +1,127 @@
+//-----------------------------
+// Dual-port RAM 1024x8 bit (8Kbit)
+// Core logic
+//-----------------------------
+module dpram_1024x8_core (
+  input wclk,
+  input wen,
+  input [0:9] waddr,
+  input [0:7] data_in,
+  input rclk,
+  input ren,
+  input [0:9] raddr,
+  output [0:7] data_out );
+
+  reg [0:7] ram[0:1023];
+  reg [0:7] internal;
+
+  assign data_out = internal;
+
+  always @(posedge wclk) begin
+    if(wen) begin
+      ram[waddr] <= data_in;
+    end
+  end
+
+  always @(posedge rclk) begin
+    if(ren) begin
+      internal <= ram[raddr];
+    end
+  end
+
+endmodule
+
+//-----------------------------
+// Dual-port RAM 1024x8 bit (8Kbit) wrapper
+// where the read clock and write clock
+// are combined to a unified clock
+//-----------------------------
+module dpram_1024x8 (
+  input clk,
+  input wen,
+  input ren,
+  input [0:9] waddr,
+  input [0:9] raddr,
+  input [0:7] data_in,
+  output [0:7] data_out );
+
+    dpram_1024x8_core memory_0 (
+      .wclk    (clk),
+      .wen    (wen),
+      .waddr    (waddr),
+      .data_in  (data_in),
+      .rclk    (clk),
+      .ren    (ren),
+      .raddr    (raddr),
+      .data_out    (data_out) );
+
+endmodule
+
+//-----------------------------
+// 36-bit multiplier
+//-----------------------------
+module mult_36(
+  input [0:35] A,
+  input [0:35] B,
+  output [0:71] Y
+);
+
+assign Y = A * B;
+
+endmodule
+
+//-----------------------------
+// Native D-type flip-flop
+//-----------------------------
+(* abc9_flop, lib_whitebox *)
+module dff(
+    output reg Q,
+    input D,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_C_INVERTED" *)
+    input C
+);
+    parameter [0:0] INIT = 1'b0;
+    parameter [0:0] IS_C_INVERTED = 1'b0;
+    initial Q = INIT;
+    case(|IS_C_INVERTED)
+          1'b0:
+            always @(posedge C)
+                Q <= D;
+          1'b1:
+            always @(negedge C)
+                Q <= D;
+    endcase
+endmodule
+
+//-----------------------------
+// D-type flip-flop with asynchronous reset
+//-----------------------------
+(* abc9_flop, lib_whitebox *)
+module dffr(
+    output reg Q,
+    input D,
+    input R,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_C_INVERTED" *)
+    input C
+);
+    parameter [0:0] INIT = 1'b0;
+    parameter [0:0] IS_C_INVERTED = 1'b0;
+    initial Q = INIT;
+    case(|IS_C_INVERTED)
+          1'b0:
+            always @(posedge C or posedge R)
+                if (R == 1'b1)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+          1'b1:
+            always @(negedge C or posedge R)
+                if (R == 1'b1)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+    endcase
+endmodule
+
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
new file mode 100644
index 000000000..822706642
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
@@ -0,0 +1,18 @@
+// Basic DFF
+module \$_DFF_P_ (D, C, Q);
+    input D;
+    input C;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
+endmodule
+
+// Async reset
+module \$_DFF_PP0_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
index 90926cef6..d4798a906 100644
--- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
@@ -93,4 +93,4 @@ module latchre (
               if (S) Q <= 1'b1;
             else if (E && G) Q <= D;
     end
-endmodule
\ No newline at end of file
+endmodule