developing routing track rr_node set up in tileable routing architecture
This commit is contained in:
tangxifan
parent
155c8d4924
commit
8c9cc003ea
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@ -61,6 +61,72 @@
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/************************************************************************
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/************************************************************************
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* Local function in the file
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* Local function in the file
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***********************************************************************/
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***********************************************************************/
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/************************************************************************
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* Initialize a rr_node
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************************************************************************/
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static
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void tileable_rr_graph_init_rr_node(t_rr_node* cur_rr_node) {
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cur_rr_node->xlow = 0;
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cur_rr_node->xhigh = 0;
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cur_rr_node->ylow = 0;
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cur_rr_node->xhigh = 0;
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cur_rr_node->ptc_num = 0;
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cur_rr_node->track_ids.clear();
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cur_rr_node->cost_index = 0;
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cur_rr_node->occ = 0;
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cur_rr_node->fan_in = 0;
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cur_rr_node->num_edges = 0;
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cur_rr_node->type = NUM_RR_TYPES;
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cur_rr_node->edges = NULL;
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cur_rr_node->switches = NULL;
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cur_rr_node->driver_switch = 0;
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cur_rr_node->unbuf_switched = 0;
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cur_rr_node->buffered = 0;
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cur_rr_node->R = 0.;
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cur_rr_node->C = 0.;
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cur_rr_node->direction = BI_DIRECTION; /* Give an invalid value, easy to check errors */
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cur_rr_node->drivers = SINGLE;
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cur_rr_node->num_wire_drivers = 0;
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cur_rr_node->num_opin_drivers = 0;
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cur_rr_node->num_drive_rr_nodes = 0;
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cur_rr_node->drive_rr_nodes = NULL;
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cur_rr_node->drive_switches = NULL;
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cur_rr_node->vpack_net_num_changed = FALSE;
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cur_rr_node->is_parasitic_net = FALSE;
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cur_rr_node->is_in_heap = FALSE;
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cur_rr_node->sb_num_drive_rr_nodes = 0;
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cur_rr_node->sb_drive_rr_nodes = NULL;
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cur_rr_node->sb_drive_switches = NULL;
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cur_rr_node->pb = NULL;
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cur_rr_node->name_mux = NULL;
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cur_rr_node->id_path = -1;
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cur_rr_node->prev_node = -1;
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cur_rr_node->prev_edge = -1;
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cur_rr_node->net_num = -1;
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cur_rr_node->vpack_net_num = -1;
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cur_rr_node->prev_node_in_pack = -1;
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cur_rr_node->prev_edge_in_pack = -1;
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cur_rr_node->net_num_in_pack = -1;
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cur_rr_node->pb_graph_pin = NULL;
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cur_rr_node->tnode = NULL;
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cur_rr_node->pack_intrinsic_cost = 0.;
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cur_rr_node->z = 0;
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return;
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}
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/************************************************************************
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/************************************************************************
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* Generate the number of tracks for each types of routing segments
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* Generate the number of tracks for each types of routing segments
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@ -398,47 +464,222 @@ std::vector<size_t> estimate_num_rr_nodes_per_type(const DeviceCoordinator& devi
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* in X-direction and Y-direction channels!!!
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* in X-direction and Y-direction channels!!!
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* So we will load segment details for different channels
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* So we will load segment details for different channels
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***********************************************************************/
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***********************************************************************/
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/* For X-direction Channel */
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/* For X-direction Channel: CHANX */
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for (size_t ix = 0; ix < grids.size() - 1; ++ix) {
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for (size_t iy = 0; iy < grids[ix].size() - 1; ++iy) {
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enum e_side chan_side = NUM_SIDES;
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/* For LEFT side of FPGA */
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/* For LEFT side of FPGA */
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ChanNodeDetails left_chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, LEFT, segment_infs);
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if (0 == ix) {
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for (size_t iy = 0; iy < device_size.get_y() - 1; ++iy) {
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chan_side = LEFT;
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num_rr_nodes_per_type[CHANX] += left_chanx_details.get_num_starting_tracks();
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}
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}
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/* For RIGHT side of FPGA */
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/* For RIGHT side of FPGA */
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ChanNodeDetails right_chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, RIGHT, segment_infs);
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if (grids.size() - 2 == ix) {
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for (size_t iy = 0; iy < device_size.get_y() - 1; ++iy) {
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chan_side = RIGHT;
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num_rr_nodes_per_type[CHANX] += right_chanx_details.get_num_starting_tracks();
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}
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}
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/* For core of FPGA */
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ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, chan_side, segment_infs);
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ChanNodeDetails core_chanx_details = build_unidir_chan_node_details(chan_width[1], device_size.get_x() - 2, NUM_SIDES, segment_infs);
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num_rr_nodes_per_type[CHANX] += chanx_details.get_num_starting_tracks();
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for (size_t ix = 1; ix < grids.size() - 2; ++ix) {
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for (size_t iy = 1; iy < grids[ix].size() - 2; ++iy) {
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num_rr_nodes_per_type[CHANX] += core_chanx_details.get_num_starting_tracks();
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}
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}
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}
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}
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/* For Y-direction Channel */
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/* For Y-direction Channel: CHANX */
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/* For TOP side of FPGA */
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for (size_t ix = 0; ix < grids.size() - 1; ++ix) {
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ChanNodeDetails top_chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, TOP, segment_infs);
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for (size_t iy = 0; iy < grids[ix].size() - 1; ++iy) {
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for (size_t ix = 0; ix < device_size.get_x() - 1; ++ix) {
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enum e_side chan_side = NUM_SIDES;
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num_rr_nodes_per_type[CHANY] += top_chany_details.get_num_starting_tracks();
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/* For LEFT side of FPGA */
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if (0 == iy) {
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chan_side = BOTTOM;
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}
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}
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/* For BOTTOM side of FPGA */
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/* For RIGHT side of FPGA */
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ChanNodeDetails bottom_chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, BOTTOM, segment_infs);
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if (grids[ix].size() - 2 == iy) {
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for (size_t ix = 0; ix < device_size.get_x() - 1; ++ix) {
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chan_side = TOP;
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num_rr_nodes_per_type[CHANY] += bottom_chany_details.get_num_starting_tracks();
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}
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}
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/* For core of FPGA */
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ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, chan_side, segment_infs);
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ChanNodeDetails core_chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, NUM_SIDES, segment_infs);
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num_rr_nodes_per_type[CHANY] += chany_details.get_num_starting_tracks();
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for (size_t ix = 1; ix < grids.size() - 2; ++ix) {
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for (size_t iy = 1; iy < grids[ix].size() - 2; ++iy) {
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num_rr_nodes_per_type[CHANY] += core_chany_details.get_num_starting_tracks();
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}
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}
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}
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}
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return num_rr_nodes_per_type;
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return num_rr_nodes_per_type;
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}
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}
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/************************************************************************
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* Configure rr_nodes for this grid
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* coordinators: xlow, ylow, xhigh, yhigh,
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* features: capacity, ptc_num (pin_num),
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***********************************************************************/
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static
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void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator,
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const t_grid_tile& cur_grid, enum e_side io_side,
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t_rr_graph* rr_graph, size_t* cur_node_id) {
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Side io_side_manager(io_side);
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/* Walk through the height of each grid,
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* get pins and configure the rr_nodes */
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for (int height = 0; height < cur_grid.type->height; ++height) {
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/* Walk through sides */
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for (size_t side = 0; side < NUM_SIDES; ++side) {
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Side side_manager(side);
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/* skip unwanted sides */
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if ( (IO_TYPE == cur_grid.type)
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&& (side != io_side_manager.to_size_t()) ) {
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continue;
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}
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/* Find OPINs */
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/* Configure pins by pins */
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std::vector<int> opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), height);
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for (size_t pin = 0; pin < opin_list.size(); ++pin) {
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/* Configure the rr_node for the OPIN */
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rr_graph->rr_node[*cur_node_id].type = OPIN;
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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(*cur_node_id)++;
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/* Set a SOURCE rr_node for the OPIN */
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rr_graph->rr_node[*cur_node_id].type = SOURCE;
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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/* TODO: should we set pb_graph_pin here? */
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(*cur_node_id)++;
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}
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/* Find IPINs */
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/* Configure pins by pins */
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std::vector<int> ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), height);
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for (size_t pin = 0; pin < ipin_list.size(); ++pin) {
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rr_graph->rr_node[*cur_node_id].type = IPIN;
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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(*cur_node_id)++;
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/* Set a SINK rr_node for the OPIN */
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rr_graph->rr_node[*cur_node_id].type = SINK;
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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/* TODO: should we set pb_graph_pin here? */
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(*cur_node_id)++;
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}
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}
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}
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return;
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}
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/************************************************************************
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* Initialize the basic information of routing track rr_nodes
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* coordinators: xlow, ylow, xhigh, yhigh,
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* features: capacity, track_ids, ptc_num, direction
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***********************************************************************/
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static
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void load_one_chan_rr_nodes_basic_info(const DeviceCoordinator& chan_coordinator,
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t_rr_type chan_type,
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const ChanNodeDetails& chan_details,
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t_rr_graph* rr_graph,
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size_t* cur_node_id) {
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return;
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}
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/************************************************************************
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* Initialize the basic information of rr_nodes:
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* coordinators: xlow, ylow, xhigh, yhigh,
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* features: capacity, track_ids, ptc_num, direction
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* grid_info : pb_graph_pin
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***********************************************************************/
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static
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void load_rr_nodes_basic_info(t_rr_graph* rr_graph,
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std::vector<size_t> num_rr_nodes_per_type,
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const DeviceCoordinator& device_size,
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std::vector<std::vector<t_grid_tile>> grids,
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std::vector<size_t> chan_width,
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std::vector<t_segment_inf> segment_infs) {
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/* counter */
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size_t cur_node_id = 0;
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/* configure by node type */
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/* SOURCE, SINK, OPIN and IPIN */
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/************************************************************************
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* Search the grid and find the number OPINs and IPINs per grid
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* Note that the number of SOURCE nodes are the same as OPINs
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* and the number of SINK nodes are the same as IPINs
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***********************************************************************/
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for (size_t ix = 0; ix < grids.size(); ++ix) {
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for (size_t iy = 0; iy < grids[ix].size(); ++iy) {
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/* Skip EMPTY tiles */
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if (EMPTY_TYPE == grids[ix][iy].type) {
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continue;
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}
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DeviceCoordinator grid_coordinator(ix, iy);
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enum e_side io_side = NUM_SIDES;
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/* If this is the block on borders, we consider IO side */
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if (IO_TYPE == grid[ix][iy].type) {
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DeviceCoordinator io_device_size(device_size.get_x() - 1, device_size.get_y() - 1);
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io_side = determine_io_grid_pin_side(device_size, grid_coordinator);
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}
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/* Configure rr_nodes for this grid */
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load_one_grid_rr_nodes_basic_info(grid_coordinator, grid[ix][iy], io_side,
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rr_graph, &cur_node_id);
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}
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}
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/* For X-direction Channel: CHANX */
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for (size_t ix = 0; ix < grids.size() - 1; ++ix) {
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for (size_t iy = 0; iy < grids[ix].size() - 1; ++iy) {
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DeviceCoordinator chan_coordinator(ix, iy);
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enum e_side chan_side = NUM_SIDES;
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/* For LEFT side of FPGA */
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if (0 == ix) {
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chan_side = LEFT;
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}
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/* For RIGHT side of FPGA */
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if (grids.size() - 2 == ix) {
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chan_side = RIGHT;
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}
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ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, chan_side, segment_infs);
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/* Configure CHANX in this channel */
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load_one_chan_rr_nodes_basic_info(chan_coordinator, CHANX, chanx_details,
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rr_graph, &cur_node_id);
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}
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}
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/* For Y-direction Channel: CHANX */
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for (size_t ix = 0; ix < grids.size() - 1; ++ix) {
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for (size_t iy = 0; iy < grids[ix].size() - 1; ++iy) {
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DeviceCoordinator chan_coordinator(ix, iy);
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enum e_side chan_side = NUM_SIDES;
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/* For LEFT side of FPGA */
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if (0 == iy) {
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chan_side = BOTTOM;
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}
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/* For RIGHT side of FPGA */
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if (grids[ix].size() - 2 == iy) {
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chan_side = TOP;
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}
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ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, chan_side, segment_infs);
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/* Configure CHANX in this channel */
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load_one_chan_rr_nodes_basic_info(chan_coordinator, CHANY, chany_details,
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rr_graph, &cur_node_id);
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}
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}
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/* Check */
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|
assert ((int)cur_node_id == rr_graph->num_rr_nodes);
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|
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||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Main function of this file
|
* Main function of this file
|
||||||
|
|
@ -541,8 +782,11 @@ t_rr_graph build_tileable_unidir_rr_graph(INP int L_num_types,
|
||||||
for (size_t i = 0; i < num_rr_nodes_per_type.size(); ++i) {
|
for (size_t i = 0; i < num_rr_nodes_per_type.size(); ++i) {
|
||||||
rr_graph.num_rr_nodes += num_rr_nodes_per_type[i];
|
rr_graph.num_rr_nodes += num_rr_nodes_per_type[i];
|
||||||
}
|
}
|
||||||
/* use calloc to initialize everything to be zero */
|
/* use calloc and memset to initialize everything to be zero */
|
||||||
rr_graph.rr_node = (t_rr_node*)my_calloc(rr_graph.num_rr_nodes, sizeof(t_rr_node));
|
rr_graph.rr_node = (t_rr_node*)my_calloc(rr_graph.num_rr_nodes, sizeof(t_rr_node));
|
||||||
|
for (int i = 0; i < rr_graph.num_rr_nodes; ++i) {
|
||||||
|
tileable_rr_graph_init_rr_node(&(rr_graph.rr_node[i]));
|
||||||
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* 4. Initialize the basic information of rr_nodes:
|
* 4. Initialize the basic information of rr_nodes:
|
||||||
|
|
@ -550,6 +794,10 @@ t_rr_graph build_tileable_unidir_rr_graph(INP int L_num_types,
|
||||||
* features: capacity, track_ids, ptc_num, direction
|
* features: capacity, track_ids, ptc_num, direction
|
||||||
* grid_info : pb_graph_pin
|
* grid_info : pb_graph_pin
|
||||||
***********************************************************************/
|
***********************************************************************/
|
||||||
|
load_rr_nodes_basic_info(&rr_graph, num_rr_nodes_per_type,
|
||||||
|
device_size, grids, device_chan_width, segment_infs);
|
||||||
|
|
||||||
|
/* build_rr_graph_fast_lookup(&rr_graph); */
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* 3. Create the connectivity of OPINs
|
* 3. Create the connectivity of OPINs
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue