Test without Verilog verification to se impact in building errors

2019-05-16 09:48:06 -06:00 · 2019-05-16 09:48:06 -06:00 · 8c9820e7ee
parent c4ccff4562
commit 8c9820e7ee
1 changed files with 1 additions and 1 deletions
--- a/.travis.yml
+++ b/.travis.yml
@ -83,7 +83,7 @@ install:

 script:
  - .travis/script.sh
-  - .travis/regression.sh
+  #- .travis/regression.sh

 after_failure:
  - .travis/after_failure.sh