started documenting architecture

jupyter_example.ipynb

@@ -4,7 +4,8 @@
    "cell_type": "markdown",
    "metadata": {},
    "source": [
-    "*Getting Started with Jupyter and FPGA-SPICE on Linux\n",
+    "# Getting Started with Jupyter and FPGA-SPICE on Linux\n",
+    "\n",
     "1. Install Anaconda: https://conda.io/docs/user-guide/install/linux.html \n",
     "2. Run anaconda-navigator: `~/anaconda-navigator`\n",
     "3. Launch jupyter notebook from anaconda navigator\n",
@@ -165,7 +166,11 @@
    "cell_type": "markdown",
    "metadata": {},
    "source": [
-    "When you ran the tool, a number of text output files are created that report on what the tool did. Open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note on line 2: \"Array size: 2 x 2 logic blocks\". This is a report that when the tool placed and routed the logic, it ended up in a 2 x 2 grid."
+    "When you ran the tool, a number of text output files are created that report on what the tool did. Open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note on line 2: \n",
+    "\n",
+    "> `Array size: 2 x 2 logic blocks`\n",
+    "\n",
+    "This is a report that when the tool placed and routed the logic, it ended up in a 2 x 2 grid."
    ]
   },
   {
@@ -209,10 +214,41 @@
    "cell_type": "markdown",
    "metadata": {},
    "source": [
-    "Re-open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note that the logic is now placed in one block.\n",
+    "Re-open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note that the logic is now placed in one block:\n",
+    "\n",
+    "> `Array size: 1 x 1 logic blocks`\n",
     "\n",
     "The simple change to the number of inputs or outputs per I/O block let the placement and routing tool use less space on the FPGA for the circuit."
    ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "# The Architecture format\n",
+    "An FPGA architecture is specified in an XML file and is wrapped in an `<architecture>` tag. `example_arch.xml` defines a simple FPGA.\n",
+    "\n",
+    "Line 18 has the `<models>` tag which would describe `BLIF` circuit model names that the FPGA accepts. This architecture is simple enough to not need any additional models beyond the default `.names .latch .input .output`.\n",
+    "\n",
+    "Line 23 has the `<layout>` tag which specifies how the FPGA grid will be laid out. For this example: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout.\n",
+    "\n",
+    "Line 24 begins the `<device>` tag which characterizes the components of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n",
+    "\n",
+    "Line 28 is the `<chan_width_distr>` section which sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distrubuted uniformly.\n",
+    "\n",
+    "Line 33 is the `<switch_block>` tag which specifies the pattern of the switches used to connect the block routing segments. \n",
+    "\n",
+    "Line 35 is the `<switchlist>` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n",
+    "\n",
+    "Line 38 is the `<segmentlist>` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `<sb type=\"pattern\">1 1</sb>` describes a pattern on a 1-length wire where there is a switch box between each grid element. `<cb type=\"pattern\">1</cb>` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {},
+   "outputs": [],
+   "source": []
   }
  ],
  "metadata": {