From 8c5ec4572d789c878deb1aac1b8864c9244471b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 7 Jun 2019 20:20:41 -0600 Subject: [PATCH] revert string to sprintf --- vpr7_x2p/libarchfpga/SRC/include/sides.h | 4 ++- vpr7_x2p/libarchfpga/SRC/sides.cpp | 26 +++++++++++++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 36 ++++++++++++++----- .../verilog/verilog_compact_netlist.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 30 ++++++++-------- 5 files changed, 71 insertions(+), 27 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/include/sides.h b/vpr7_x2p/libarchfpga/SRC/include/sides.h index b029d1322..4af4d3656 100644 --- a/vpr7_x2p/libarchfpga/SRC/include/sides.h +++ b/vpr7_x2p/libarchfpga/SRC/include/sides.h @@ -7,6 +7,7 @@ * This class aims to provide a easy proctol for manipulating a side */ #include +#include /* Orientations. */ enum e_side { @@ -29,7 +30,8 @@ class Side { enum e_side get_rotate_counterclockwise() const; bool validate() const; size_t to_size_t() const; - char* to_string() const; + const char* c_str() const; + std::string to_string() const; public: /* Mutators */ void set_side(size_t side); void set_side(enum e_side side); diff --git a/vpr7_x2p/libarchfpga/SRC/sides.cpp b/vpr7_x2p/libarchfpga/SRC/sides.cpp index 20f841a9a..5cbf061ba 100644 --- a/vpr7_x2p/libarchfpga/SRC/sides.cpp +++ b/vpr7_x2p/libarchfpga/SRC/sides.cpp @@ -88,7 +88,7 @@ size_t Side::to_size_t() const { } /* Convert to char* */ -char* Side::to_string() const { +const char* Side::c_str() const { switch (side_) { case TOP: return "top"; @@ -103,6 +103,30 @@ char* Side::to_string() const { } } +/* Convert to char* */ +std::string Side::to_string() const { + std::string ret; + switch (side_) { + case TOP: + ret.assign("top"); + break; + case RIGHT: + ret.assign("right"); + break; + case BOTTOM: + ret.assign("bottom"); + break; + case LEFT: + ret.assign("left"); + break; + default: + ret.assign("invalid_side"); + break; + } + + return ret; +} + /* Public Mutators */ void Side::set_side(size_t side) { switch (side) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 15b47d6c3..a22be95a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -1366,17 +1366,32 @@ const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_ sprintf(ret, "%s_%s_seg_%s_", prefix.c_str(), side_str.c_str(), seg_id_str.c_str()); return ret; + /* FIXME Have no clue why the following c++ code is not working + std::string ret(prefix); + ret.append("_"); + ret.append(side_str); + ret.append("_seg_"); + ret.append(seg_id_str); + ret.append("_"); + + return ret.c_str(); + */ } const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const { std::string prefix(gen_sb_verilog_side_module_name(side, seg_id)); - char* ret = NULL; ret = (char*) my_malloc (prefix.length() + 3 + 1); sprintf(ret, "%s_0_", prefix.c_str()); - + return ret; + /* FIXME Have no clue why the following c++ code is not working + std::string ret(prefix); + ret.append("_0_"); + + return ret.c_str(); + */ } /* Public Accessors Verilog writer */ @@ -1387,8 +1402,13 @@ const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const { std::string x_str = std::to_string(get_cb_x(cb_type)); std::string y_str = std::to_string(get_cb_y(cb_type)); - std::string ret = convert_cb_type_to_string(cb_type); - ret = "_" + x_str + "__" + y_str + "_"; + std::string ret; + ret.append(convert_cb_type_to_string(cb_type)); + ret.append("_"); + ret.append(x_str); + ret.append("__"); + ret.append(y_str); + ret.append("_"); return ret.c_str(); } @@ -1397,13 +1417,11 @@ const char* RRGSB::gen_cb_verilog_instance_name(t_rr_type cb_type) const { /* check */ assert (validate_cb_type(cb_type)); - std::string x_str = std::to_string(get_cb_x(cb_type)); - std::string y_str = std::to_string(get_cb_y(cb_type)); - - std::string ret = convert_cb_type_to_string(cb_type); - ret = "_" + x_str + "__" + y_str + "__0_"; + std::string ret(gen_cb_verilog_module_name(cb_type)); + ret.append("_0_"); return ret.c_str(); + } /* Public mutators */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index f520b19a6..53c10f17b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -781,7 +781,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); - fprintf(fp, "//----- %s side channel ports-----\n", side_manager.to_string()); + fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { fprintf(fp, "%s,\n", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 5502e9f57..aca923d85 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1683,7 +1683,7 @@ size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sr default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port Channel node[%s] track[%d]!\n", - __FILE__, __LINE__, side_manager.to_string(), itrack); + __FILE__, __LINE__, side_manager.c_str(), itrack); exit(1); } } @@ -1764,7 +1764,7 @@ size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_i default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port Channel node[%s] track[%d]!\n", - __FILE__, __LINE__, side_manager.to_string(), itrack); + __FILE__, __LINE__, side_manager.c_str(), itrack); exit(1); } } @@ -1842,7 +1842,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); /* Print ports */ - fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.to_string()); + fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { @@ -1966,10 +1966,10 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Create file name */ std::string fname_prefix(sb_verilog_file_name_prefix); - fname_prefix += side_manager.to_string(); + fname_prefix += side_manager.c_str(); std::string file_description("Unique module for Switch Block side: "); - file_description += side_manager.to_string(); + file_description += side_manager.c_str(); file_description += "seg"; file_description += std::to_string(seg_id); @@ -1983,7 +1983,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Comment lines */ fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.to_string(), seg_id); + rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str(), seg_id); /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); /* dump global ports */ @@ -2030,7 +2030,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Put down all the multiplexers */ fprintf(fp, "//----- %s side Multiplexers -----\n", - side_manager.to_string()); + side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); @@ -2051,7 +2051,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Comment lines */ fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.to_string()); + rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str()); /* Check */ assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); @@ -2125,7 +2125,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); /* Print ports */ - fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.to_string()); + fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str()); DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { @@ -2150,7 +2150,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ - fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.to_string()); + fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str()); for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2206,12 +2206,12 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); fprintf(fp, "//----- %s side Submodule -----\n", - side_manager.to_string()); + side_manager.c_str()); /* Get the channel width on this side, if it is zero, we return */ if (0 == rr_sb.get_chan_width(side_manager.get_side())) { fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n", - side_manager.to_string()); + side_manager.c_str()); continue; } @@ -2219,7 +2219,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or std::vector seg_ids = rr_sb.get_chan(side_manager.get_side()).get_segment_ids(); for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n", - side_manager.to_string(), seg_ids[iseg]); + side_manager.c_str(), seg_ids[iseg]); /* Count the number of configuration bits to be consumed by this Switch block */ int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side_manager.get_side(), seg_ids[iseg]); @@ -2367,7 +2367,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); /* Print ports */ - fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.to_string()); + fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { @@ -2442,7 +2442,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); fprintf(fp, "//----- %s side Multiplexers -----\n", - side_manager.to_string()); + side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type));