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[core] debuggging

This commit is contained in:
tangxifan 2024-06-28 23:06:21 -07:00
parent 1c69365938
commit 8bc37080fa
2 changed files with 5 additions and 3 deletions
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4
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -59,6 +59,7 @@ static int build_clock_tree_net_map(
clk_ntwk.tree_width(clk_tree)); clk_ntwk.tree_width(clk_tree));
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }
/* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */
/* Register the pin mapping */ /* Register the pin mapping */
tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet;
} }
@ -457,7 +458,8 @@ int route_clock_rr_graph(
const DeviceContext& vpr_device_ctx, const DeviceContext& vpr_device_ctx,
const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx,
const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk,
const PinConstraints& pin_constraints, const bool& disable_unused_trees, const PinConstraints& pin_constraints,
const bool& disable_unused_trees,
const bool& disable_unused_spines, const bool& verbose) { const bool& disable_unused_spines, const bool& verbose) {
vtr::ScopedStartFinishTimer timer( vtr::ScopedStartFinishTimer timer(
"Route programmable clock network based on routing resource graph"); "Route programmable clock network based on routing resource graph");

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
View File

@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_verilog_testbench_port_mapping= bench0_openfpga_verilog_testbench_port_mapping=
bench1_top = counter bench1_top = counter
bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
bench1_openfpga_verilog_testbench_port_mapping= bench1_openfpga_verilog_testbench_port_mapping=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]