riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bug fixing for mux subckt names

This commit is contained in:
tangxifan 2019-07-17 08:59:57 -06:00
parent a2505ff16a
commit 8b8e18a8de
3 changed files with 26 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1128,9 +1128,9 @@ void dump_verilog_mux_basis_module(FILE* fp,
/* Prepare the basis subckt name: /* Prepare the basis subckt name:
*/ */
mux_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix); mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix);
special_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix); special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix);
/* deteremine the number of inputs of basis subckt */ /* deteremine the number of inputs of basis subckt */
num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis;
@ -1647,9 +1647,9 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
char* mux_basis_subckt_name = NULL; char* mux_basis_subckt_name = NULL;
char* mux_special_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL;
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
/* Make sure we have a valid file handler*/ /* Make sure we have a valid file handler*/
if (NULL == fp) { if (NULL == fp) {
@ -2156,9 +2156,9 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
char* mux_basis_subckt_name = NULL; char* mux_basis_subckt_name = NULL;
char* mux_special_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL;
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
/* Make sure we have a valid file handler*/ /* Make sure we have a valid file handler*/
if (NULL == fp) { if (NULL == fp) {

16
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2915,9 +2915,8 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
return subckt_name; return subckt_name;
} }
/* Generate the subckt name for a MUX module/submodule */ /* Generate the subckt name for a MUX module/submodule */
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix) { int mux_size, char* postfix) {
char* mux_subckt_name = NULL; char* mux_subckt_name = NULL;
@ -2928,11 +2927,22 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type); assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type);
mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name);
} else { } else {
mux_subckt_name = generate_verilog_mux_subckt_name(spice_model, mux_size, postfix);
}
return mux_subckt_name;
}
/* Generate the subckt name for a MUX module/submodule */
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix) {
char* mux_subckt_name = NULL;
mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5
+ strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); + strlen(my_itoa(mux_size)) + strlen(postfix) + 1));
sprintf(mux_subckt_name, "%s_size%d%s", sprintf(mux_subckt_name, "%s_size%d%s",
spice_model->name, mux_size, postfix); spice_model->name, mux_size, postfix);
}
return mux_subckt_name; return mux_subckt_name;
} }

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -221,6 +221,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
t_spice_model* mem_model, t_spice_model* mem_model,
char* postfix); char* postfix);
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix);
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix); int mux_size, char* postfix);