riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow

This commit is contained in:
Lalit Sharma 2021-01-08 07:08:24 -08:00
parent 0bb1f92ed8
commit 8a5741b1ae
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
View File

@ -2,5 +2,5 @@
# Read verilog files # Read verilog files
${READ_VERILOG_FILE} ${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE} synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE}

2
yosys

@ -1 +1 @@
Subproject commit aec2c41441bffa981092095d25655e80dae6ef06 Subproject commit a0606e09f57df456ba9bcfc6a7cf7b64d814b8e4