diff --git a/openfpga/src/annotation/annotate_physical_tiles.cpp b/openfpga/src/annotation/annotate_physical_tiles.cpp
index f53790b99..27db35461 100644
--- a/openfpga/src/annotation/annotate_physical_tiles.cpp
+++ b/openfpga/src/annotation/annotate_physical_tiles.cpp
@@ -48,9 +48,7 @@ void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx,
           }
         }
         /* Count the number of pins for each sub tile */
-        for (const t_physical_tile_port& tile_port : sub_tile.ports) {
-          curr_pin_index += tile_port.num_pins;
-        }
+        curr_pin_index += sub_tile.num_phy_pins / sub_tile.capacity.total();
       }
     }
   }
diff --git a/openfpga/src/fabric/build_fabric_io_location_map.cpp b/openfpga/src/fabric/build_fabric_io_location_map.cpp
index 36422f44d..d5ae48c1d 100644
--- a/openfpga/src/fabric/build_fabric_io_location_map.cpp
+++ b/openfpga/src/fabric/build_fabric_io_location_map.cpp
@@ -132,6 +132,7 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
        * that GPIOs are wired in function connect_gpio_module()
        *
        * Note: if you change the GPIO function, you should update here as well!
+       * FIXME: The codes should be adapt to support sub tiles!!!
        */
       for (int z = 0; z < grids[ix][iy].type->capacity; ++z) {
         for (const ModuleManager::e_module_port_type& module_io_port_type : MODULE_IO_PORT_TYPES) {
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index 24b486dbe..d0a65ad6b 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit 24b486dbe28246f6285cfb86af82628f93229491
+Subproject commit d0a65ad6b86ae312d8a34fa3954656de3a4f1252