From 889bc8dbe82999372ce41dda188b7d55c1ceaa94 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 May 2020 15:05:59 -0600 Subject: [PATCH] add more test cases about LUT design and deploy to CI --- .travis/script.sh | 11 +- ..._N10_intermediate_buffer_40nm_openfpga.xml | 229 ++++++++++++++++++ .../frac_lut/config/task.conf | 0 .../intermediate_buffer/config/task.conf | 45 ++++ .../single_mode/config/task.conf | 0 5 files changed, 281 insertions(+), 4 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml rename openfpga_flow/tasks/openfpga_shell/{ => lut_design}/frac_lut/config/task.conf (100%) create mode 100644 openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf rename openfpga_flow/tasks/openfpga_shell/{ => lut_design}/single_mode/config/task.conf (100%) diff --git a/.travis/script.sh b/.travis/script.sh index cb9601683..19da16b8b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -51,11 +51,14 @@ echo -e "Testing OpenFPGA Shell"; echo -e "Testing configuration chain of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs -echo -e "Testing Verilog generation for a single mode LUT6 FPGA using micro benchmarks"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/single_mode --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/single_mode --debug --show_thread_logs -echo -e "Testing Verilog generation with simple fracturable LUT6 "; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/frac_lut --debug --show_thread_logs + +echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/intermediate_buffer --debug --show_thread_logs echo -e "Testing Verilog generation with VPR's untileable routing architecture "; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml new file mode 100644 index 000000000..ef1c60a80 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -0,0 +1,229 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf similarity index 100% rename from openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf rename to openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf new file mode 100644 index 000000000..b2535bd7c --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml + +[BENCHMARKS] +# +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif +# Modelsim is ok with this but icarus fails due to poor support on timing and looping +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +bench1_top = routing_test +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v + +bench2_top = and2_latch +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf similarity index 100% rename from openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf rename to openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf