diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index f4888c25f..0ea4fc420 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -288,8 +288,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); } - /* dump_verilog_sdc_file(); */ - /* dump verilog testbench only for input blif */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench) { blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 495184f34..c8f5088ec 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -1016,6 +1016,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -unconstrained"); break; + /* All the types are verified before */ default: break; } @@ -1062,6 +1063,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1107,6 +1111,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1152,6 +1159,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1185,7 +1195,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; - int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; @@ -1368,6 +1377,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1403,6 +1414,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1438,6 +1451,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1473,12 +1488,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } } - if (NULL != rpt_name) { + if (NULL != rpt_name) { fprintf(fp, " > %s\n", rpt_name); } else { fprintf(fp, "\n"); @@ -1490,516 +1507,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, return; } -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// const RRGSB& src_sb, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// char* rpt_name = NULL; -// DeviceCoordinator next_sb_coordinator; -// RRGSB next_sb; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); -// next_sb = device_rr_gsb.get_gsb(next_sb_coordinator); -// end_sb_x = next_sb.get_sb_x(); -// end_sb_y = next_sb.get_sb_y(); -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb.get_sb_x(); -// cur_sb_y = src_sb.get_sb_y(); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x(); ix < end_sb_x; ix++) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y(); iy < end_sb_y; iy++) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x() - 1; ix > end_sb_x; ix--) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y() - 1; iy > end_sb_y; iy--) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} -// -// -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// t_sb* src_sb_info, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int ix, iy; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// t_sb* next_sb = NULL; -// char* rpt_name = NULL; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb_info, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node); -// end_sb_x = next_sb->x; -// end_sb_y = next_sb->y; -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb_info->x; -// cur_sb_y = src_sb_info->y; -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x; ix < end_sb_x; ix++) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix + 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y; iy < end_sb_y; iy++) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy + 1]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x - 1; ix > end_sb_x; ix--) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix - 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y - 1; iy > end_sb_y; iy--) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy - 1]), src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} - /* Print the pins of SBs that a routing wire will go through * from the src_rr_node to the des_rr_node */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index abdfbba53..6e21f776e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -958,6 +958,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); + fprintf(fp, ".%s(", + cur_global_port->prefix); if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), @@ -968,6 +970,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, cur_global_port->prefix, cur_global_port->size - 1); } + fprintf(fp, ")"); + /* if this is the tail, we do not dump a comma */ if (NULL != temp->next) { fprintf(fp, ", //---- global port \n");