diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst
index 3f41f1a1d..addf4496f 100644
--- a/docs/source/manual/fpga_verilog/testbench.rst
+++ b/docs/source/manual/fpga_verilog/testbench.rst
@@ -87,23 +87,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
    - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. 
 
    .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
-
-   - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command. 
-
-   .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
-
-   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
    
-   - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command. 
-
-   .. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
-
-__ iverilog_website_
-
-.. _iverilog_website: http://iverilog.icarus.com/
-
-
-
 .. option:: <bench_name>_autocheck_top_tb.v
 
   This is the netlist for full testbench.
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
index 88cf33bc6..d8e254a3e 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
@@ -76,6 +76,11 @@ write_full_testbench
 
     Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
 
+    .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+
+   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
+
+
   .. option:: --verbose
 
     Show verbose log
@@ -106,14 +111,26 @@ write_preconfigured_fabric_wrapper
 
     Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
 
-  .. option:: --support_icarus_simulator
+  .. option:: --embed_bitstream <string>
      
-    Output Verilog netlists with syntax that iVerilog simulator can accept
+    Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``.
+
+    .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
+
+   .. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
+
+__ iverilog_website_
+
+.. _iverilog_website: http://iverilog.icarus.com/
 
   .. option:: --include_signal_init
 
     Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
 
+    .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+
+   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
+
   .. option:: --verbose
 
     Show verbose log
@@ -148,10 +165,6 @@ write_preconfigured_testbench
 
     Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
 
-  .. option:: --support_icarus_simulator
-     
-    Output Verilog netlists with syntax that iVerilog simulator can accept
-
   .. option:: --verbose
 
     Show verbose log
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 3821c407f..b912c518c 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -130,8 +130,8 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_default_net_type = cmd.option("default_net_type");
-  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
+  CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -142,13 +142,17 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
   options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
-  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
   options.set_print_formal_verification_top_netlist(true);
+
   if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
     options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
   }
 
+  if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) {
+    options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream));
+  }
+
   /* If pin constraints are enabled by command options, read the file */
   PinConstraints pin_constraints;
   if (true == cmd_context.option_enable(cmd, opt_pcf)) {
@@ -178,7 +182,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
   CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
-  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_default_net_type = cmd.option("default_net_type");
   CommandOptionId opt_verbose = cmd.option("verbose");
@@ -190,7 +193,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
   options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
   options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
   options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
-  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_print_preconfig_top_testbench(true);
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index c78d69595..95c146e03 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -146,8 +146,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
   CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
   shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
 
-  /* Add an option '--support_icarus_simulator' */
-  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
+  /* Add an option '--embed_bitstream' */
+  CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size");
+  shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING);
 
   /* add an option '--include_signal_init' */
   shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
@@ -195,9 +196,6 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
   CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
   shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
 
-  /* Add an option '--support_icarus_simulator' */
-  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
-
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index e3675428d..02fbaa166 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -365,7 +365,7 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
                                                        const CircuitLibrary& circuit_lib,
                                                        const CircuitModelId& mem_model,
                                                        const BitstreamManager &bitstream_manager,
-                                                       const bool& support_icarus_simulator) {
+                                                       const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) {
 
   /* Skip the datab port if there is only 1 output port in memory model
    * Currently, it assumes that the data output port is always defined while datab is optional
@@ -381,12 +381,13 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
   print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
 
   /* Use assign syntax for Icarus simulator */
-  if (support_icarus_simulator) {
+  if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
     print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
                                                         bitstream_manager,
                                                         output_datab_bits);
   } else {
     /* Use deposit syntax for other simulators */
+    VTR_ASSERT(EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type);
     print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
                                                          bitstream_manager,
                                                          output_datab_bits);
@@ -499,11 +500,11 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
   CircuitModelId sram_model = config_protocol.memory_model();  
   VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model));
 
-  /* Assign FPGA internal SRAM/Memory ports to bitstream values */
+  /* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */
   print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
                                                     circuit_lib, sram_model, 
                                                     bitstream_manager,
-                                                    options.support_icarus_simulator());
+                                                    options.embedded_bitstream_hdl_type());
 
   /* Add signal initialization: 
    * Bypass writing codes to files due to the autogenerated codes are very large.
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index 49d14dee6..ca936bea7 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -21,9 +21,9 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
   print_top_testbench_ = false;
   simulation_ini_path_.clear();
   explicit_port_mapping_ = false;
-  support_icarus_simulator_ = false;
   include_signal_init_ = false;
   default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
+  embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
   time_unit_ = 1E-3;
   verbose_output_ = false;
 }
@@ -75,10 +75,6 @@ bool VerilogTestbenchOption::include_signal_init() const {
   return include_signal_init_;
 }
 
-bool VerilogTestbenchOption::support_icarus_simulator() const {
-  return support_icarus_simulator_;
-}
-
 e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
   return default_net_type_;
 }
@@ -87,6 +83,10 @@ float VerilogTestbenchOption::time_unit() const {
   return time_unit_;
 }
 
+e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const {
+  return embedded_bitstream_hdl_type_; 
+}
+
 bool VerilogTestbenchOption::verbose_output() const {
   return verbose_output_;
 }
@@ -147,10 +147,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
   include_signal_init_ = enabled;
 }
 
-void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) {
-  support_icarus_simulator_ = enabled;
-}
-
 void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
   /* Decode from net type string */;
   if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {
@@ -165,6 +161,23 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net
   }
 }
 
+void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) {
+  /* Decode from HDL type string */;
+  if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) {
+    embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES;
+  } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) {
+    embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG;
+  } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) {
+    embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
+  } else {
+    VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n",
+                 embedded_bitstream_hdl_type.c_str(),
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES],
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG],
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]);
+  }
+}
+
 void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
   time_unit_ = time_unit;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index a68a44bd2..ad671386d 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -10,6 +10,15 @@
 /* Begin namespace openfpga */
 namespace openfpga {
 
+/* Embedded bitstream code style */
+enum e_embedded_bitstream_hdl_type {
+  EMBEDDED_BITSTREAM_HDL_IVERILOG,
+  EMBEDDED_BITSTREAM_HDL_MODELSIM,
+  NUM_EMBEDDED_BITSTREAM_HDL_TYPES
+};
+
+constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1> EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types
+
 /********************************************************************
  * Options for Verilog Testbench generator
  * Typicall usage:
@@ -34,8 +43,8 @@ class VerilogTestbenchOption {
     std::string simulation_ini_path() const;
     bool explicit_port_mapping() const;
     bool include_signal_init() const;
-    bool support_icarus_simulator() const;
     e_verilog_default_net_type default_net_type() const;
+    e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
     float time_unit() const;
     bool verbose_output() const;
   public: /* Public validator */
@@ -60,9 +69,9 @@ class VerilogTestbenchOption {
     void set_print_simulation_ini(const std::string& simulation_ini_path);
     void set_explicit_port_mapping(const bool& enabled);
     void set_include_signal_init(const bool& enabled);
-    void set_support_icarus_simulator(const bool& enabled);
     void set_default_net_type(const std::string& default_net_type);
     void set_time_unit(const float& time_unit);
+    void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -75,9 +84,9 @@ class VerilogTestbenchOption {
     /* Print simulation ini is enabled only when the path is not empty */
     std::string simulation_ini_path_;
     bool explicit_port_mapping_;
-    bool support_icarus_simulator_;
     bool include_signal_init_;
     e_verilog_default_net_type default_net_type_;
+    e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
     float time_unit_;
     bool verbose_output_;
 };
diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
index cf614678e..be124317b 100644
--- a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
@@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping  --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
 
 # Finish and exit OpenFPGA
 exit
diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
index 2d4820510..d0e0d69e2 100644
--- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
@@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
index 34e56c3b9..00944653e 100644
--- a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
@@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga
index cf9cbd8b5..55c54adb7 100644
--- a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga
@@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
index 71e6fd224..a31f81948 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit 
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
index 61c5ea8af..e614455cf 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
index 94a9a41c5..594d2e21b 100644
--- a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
index ea4f9912e..4a826bffe 100644
--- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
@@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
index c40e79c79..1e1db546d 100644
--- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
@@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
index fe7679f65..7ca431e92 100644
--- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
index 79430e976..9f2742315 100644
--- a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
index 4511ba34d..2fc56e4c7 100644
--- a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
index 571ceee8f..6efc2baa5 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
@@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
index 857b20981..4dd7f21c3 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
@@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
index 19487e48b..b0322f105 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
@@ -52,8 +52,8 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
index bc56dc8ee..db51ffe15 100644
--- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
@@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
index 5fe8cd4b5..ff0ba8d81 100644
--- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
@@ -62,8 +62,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
index 9a32a86eb..31296021f 100644
--- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga
index d44e57a24..1741f3011 100644
--- a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
index 7f2984f96..78daebb4b 100644
--- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
@@ -54,8 +54,8 @@ write_fabric_verilog --file ./SRC \
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} 
 
 # Finish and exit OpenFPGA
 exit
diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh
index 6b568e5d8..c222fa6d5 100644
--- a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh
+++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh
@@ -1,4 +1,12 @@
 foreach i (*.openfpga)
-    sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
-    sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
+#    sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
+#    sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
+end
+
+foreach i (*.openfpga)
+    sed -i 's/--support_icarus_simulator//g' $i
+end
+
+foreach i (*.openfpga)
+    sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i
 end
diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga
index 7cfe311f3..7dd793dbe 100644
--- a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga
index fab25be5a..3dc4da3da 100644
--- a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} 
-write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} 
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} 
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping  --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here