From 86c856d35a25cb55045e52a4117dd4988d53d295 Mon Sep 17 00:00:00 2001 From: bbleaptrot <35536624+bbleaptrot@users.noreply.github.com> Date: Mon, 19 Apr 2021 09:25:54 -0600 Subject: [PATCH] Fix reference links --- .../tutorials/arch_modeling/user_defined_temp_tutorial.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst index a1b59d27e..ea874f15f 100644 --- a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst +++ b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst @@ -5,7 +5,7 @@ Introduction and Setup **In this tutorial, we will** - Provide the motivation for generating the user_defined_template.v verilog file - Go through a generated user_defined_template.v file to demonstrate how to use it -Through this tutorial, we will show how and when to use the :ref:`user_defined_templates.v ` file. +Through this tutorial, we will show how and when to use the :ref:`user_defined_template.v ` file. To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA. To follow along, go to the root directory of OpenFPGA and enter: @@ -74,7 +74,7 @@ This error can be resolved by replacing the **LINE187** of ``k6_frac_N10_adder_c -The above line provides a path to generate the :ref:`user_defined_templates.v ` file. +The above line provides a path to generate the :ref:`user_defined_template.v ` file. Now we can return to the root directory and run this command again: .. code-block:: bash @@ -85,7 +85,7 @@ The task should now complete without any errors. Fixing the Error with user_defined_template.v ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The :ref:`user_defined_templates.v ` file can be found starting from the root directory and entering: +The :ref:`user_defined_template.v ` file can be found starting from the root directory and entering: .. code-block:: bash