add fabric bitstream generation online
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tangxifan
parent
8723007f68
commit
86c7c24701
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/********************************************************************
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* This file includes functions to build fabric dependent bitstream
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*******************************************************************/
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#include <string>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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#include "openfpga_naming.h"
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#include "bitstream_manager_utils.h"
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#include "build_fabric_bitstream.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function will walk through all the configurable children under a module
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* in a recursive way, following a Depth-First Search (DFS) strategy
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* For each configuration child, we use its instance name as a key to spot the
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* configuration bits in bitstream manager.
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* Note that it is guarentee that the instance name in module manager is
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* consistent with the block names in bitstream manager
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* We use this link to reorganize the bitstream in the sequence of memories as we stored
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* in the configurable_children) and configurable_child_instances() of each module of module manager
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*******************************************************************/
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static
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void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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const ConfigBlockId& parent_block,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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std::vector<ConfigBitId>& fabric_bitstream) {
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/* Depth-first search: if we have any children in the parent_block,
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* we dive to the next level first!
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*/
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if (0 < bitstream_manager.block_children(parent_block).size()) {
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for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) {
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ModuleId child_module = module_manager.configurable_children(parent_module)[child_id];
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size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id];
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/* Get the instance name and ensure it is not empty */
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std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
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/* Find the child block that matches the instance name! */
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ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name);
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/* We must have one valid block id! */
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if (true != bitstream_manager.valid_block_id(child_block))
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VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
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/* Go recursively */
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rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block,
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module_manager, child_module,
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fabric_bitstream);
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}
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/* Ensure that there should be no configuration bits in the parent block */
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VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
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}
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/* Note that, reach here, it means that this is a leaf node.
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* We add the configuration bits to the fabric_bitstream,
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* And then, we can return
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*/
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for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
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fabric_bitstream.push_back(config_bit);
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}
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}
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/********************************************************************
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* A top-level function re-organizes the bitstream for a specific
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* FPGA fabric, where configuration bits are organized in the sequence
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* that can be directly loaded to the FPGA configuration protocol.
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* Support:
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* 1. Configuration chain
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* 2. Memory decoders
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* This function does NOT modify the bitstream database
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* Instead, it builds a vector of ids for configuration bits in bitstream manager
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*
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* This function can be called ONLY after the function build_device_bitstream()
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* Note that this function does NOT decode bitstreams from circuit implementation
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* It was done in the function build_device_bitstream()
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*******************************************************************/
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std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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const ModuleManager& module_manager) {
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std::vector<ConfigBitId> fabric_bitstream;
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vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
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/* Get the top module name in module manager, which is our starting point */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Find the top block in bitstream manager, which has not parents */
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std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
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/* Make sure we have only 1 top block and its name matches the top module */
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VTR_ASSERT(1 == top_block.size());
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VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
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rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0],
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module_manager, top_module,
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fabric_bitstream);
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/* Time-consuming sanity check: Uncomment these codes only for debugging!!!
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* Check which configuration bits are not touched
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*/
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/*
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for (const ConfigBitId& config_bit : bitstream_manager.bits()) {
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std::vector<ConfigBitId>::iterator it = std::find(fabric_bitstream.begin(), fabric_bitstream.end(), config_bit);
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if (it == fabric_bitstream.end()) {
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std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bitstream_manager.bit_parent_block(config_bit));
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std::string block_hierarchy_name;
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for (const ConfigBlockId& temp_block : block_hierarchy) {
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block_hierarchy_name += std::string("/") + bitstream_manager.block_name(temp_block);
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}
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vpr_printf(TIO_MESSAGE_INFO,
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"bit (parent_block = %s) is not touched!\n",
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block_hierarchy_name.c_str());
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}
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}
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*/
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/* Ensure our fabric bitstream is in the same size as device bistream */
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VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
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return fabric_bitstream;
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}
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} /* end namespace openfpga */
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@ -0,0 +1,23 @@
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#ifndef BUILD_FABRIC_BITSTREAM_H
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#define BUILD_FABRIC_BITSTREAM_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <vector>
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#include "bitstream_manager.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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const ModuleManager& module_manager);
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} /* end namespace openfpga */
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#endif
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