riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

remove unused codes and parameters

This commit is contained in:
tangxifan 2019-12-24 20:43:29 -07:00
parent 5445047863
commit 868c573e59
15 changed files with 40 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp
View File

@ -27,7 +27,6 @@
*******************************************************************/
static
void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const RRGSB& rr_gsb,
@ -223,7 +222,6 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
*******************************************************************/
static
void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const t_rr_type& cb_type,
@ -242,7 +240,7 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
continue;
}
print_analysis_sdc_disable_cb_unused_resources(fp, grids,
print_analysis_sdc_disable_cb_unused_resources(fp,
module_manager,
L_device_rr_gsb,
rr_gsb,
@ -257,16 +255,15 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
* and disable unused ports for each of them
*******************************************************************/
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const bool& compact_routing_hierarchy) {
print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager,
print_analysis_sdc_disable_unused_cb_ports(fp, module_manager,
L_device_rr_gsb,
CHANX, compact_routing_hierarchy);
print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager,
print_analysis_sdc_disable_unused_cb_ports(fp, module_manager,
L_device_rr_gsb,
CHANY, compact_routing_hierarchy);
}
@ -279,7 +276,6 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
*******************************************************************/
static
void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const RRGSB& rr_gsb,
@ -518,7 +514,6 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
* and disable unused ports for each of them
*******************************************************************/
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const bool& compact_routing_hierarchy) {
@ -534,7 +529,7 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
*/
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
print_analysis_sdc_disable_sb_unused_resources(fp, grids,
print_analysis_sdc_disable_sb_unused_resources(fp,
module_manager,
L_device_rr_gsb,
rr_gsb,

2
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h
View File

@ -8,13 +8,11 @@
#include "vpr_types.h"
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const bool& compact_routing_hierarchy);
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const std::vector<std::vector<t_grid_tile>>& grids,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const bool& compact_routing_hierarchy);

4
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp
View File

@ -244,13 +244,13 @@ void print_analysis_sdc(const std::string& sdc_dir,
/* Disable timing for unused routing resources in connection blocks */
print_analysis_sdc_disable_unused_cbs(fp, L_grids,
print_analysis_sdc_disable_unused_cbs(fp,
module_manager,
L_device_rr_gsb,
compact_routing_hierarchy);
/* Disable timing for unused routing resources in switch blocks */
print_analysis_sdc_disable_unused_sbs(fp, L_grids,
print_analysis_sdc_disable_unused_sbs(fp,
module_manager,
L_device_rr_gsb,
compact_routing_hierarchy);

28
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp
View File

@ -43,7 +43,6 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const e_side& output_node_side,
t_rr_node* output_rr_node) {
@ -70,7 +69,6 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
std::vector<ModulePortId> module_input_ports = find_switch_block_module_input_ports(module_manager,
sb_module,
rr_gsb,
grids,
input_rr_nodes);
/* Find timing constraints for each path (edge) */
@ -103,7 +101,6 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
static
void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const RRGSB& rr_gsb) {
@ -141,7 +138,7 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
print_pnr_sdc_constrain_sb_mux_timing(fp,
module_manager, sb_module,
rr_gsb,
grids, switches,
switches,
side_manager.get_side(),
chan_rr_node);
}
@ -157,7 +154,6 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
*******************************************************************/
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb) {
vpr_printf(TIO_MESSAGE_INFO,
@ -174,7 +170,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
print_pnr_sdc_constrain_sb_timing(sdc_dir,
module_manager,
grids, switches,
switches,
rr_gsb);
}
}
@ -194,7 +190,6 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
*******************************************************************/
void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb) {
vpr_printf(TIO_MESSAGE_INFO,
@ -207,7 +202,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb);
print_pnr_sdc_constrain_sb_timing(sdc_dir,
module_manager,
grids, switches,
switches,
rr_gsb);
}
@ -230,7 +225,6 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
const ModuleId& cb_module,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
t_rr_node* output_rr_node) {
/* Validate file stream */
@ -251,7 +245,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager,
cb_module,
rr_gsb,
grids, output_rr_node);
output_rr_node);
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<t_rr_node*> input_rr_nodes;
@ -295,7 +289,6 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches) {
/* Create the netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
@ -327,7 +320,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
print_pnr_sdc_constrain_cb_mux_timing(fp,
module_manager, cb_module,
rr_gsb, cb_type,
grids, switches,
switches,
ipin_rr_node);
}
}
@ -344,7 +337,6 @@ static
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const t_rr_type& cb_type) {
/* Build unique X-direction connection block modules */
@ -364,7 +356,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
module_manager,
rr_gsb,
cb_type,
grids, switches);
switches);
}
}
@ -377,7 +369,6 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches) {
vpr_printf(TIO_MESSAGE_INFO,
"Generating SDC for constrain Connection Block timing for P&R flow...");
@ -387,13 +378,11 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager,
L_device_rr_gsb,
grids,
switches,
CHANX);
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager,
L_device_rr_gsb,
grids,
switches,
CHANY);
@ -412,7 +401,6 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
*******************************************************************/
void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb) {
vpr_printf(TIO_MESSAGE_INFO,
@ -428,7 +416,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
module_manager,
unique_mirror,
CHANX,
grids, switches);
switches);
}
/* Print SDC for unique Y-direction connection block modules */
@ -438,7 +426,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
module_manager,
unique_mirror,
CHANY,
grids, switches);
switches);
}
/* End time count */

4
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h
View File

@ -9,25 +9,21 @@
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb);
void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb);
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches);
void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
const ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb);

7
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp
View File

@ -387,7 +387,6 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
*******************************************************************/
void print_pnr_sdc(const SdcOption& sdc_options,
const float& critical_path_delay,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb,
const ModuleManager& module_manager,
@ -436,13 +435,13 @@ void print_pnr_sdc(const SdcOption& sdc_options,
if (true == compact_routing_hierarchy) {
print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
module_manager,
grids, switches,
switches,
L_device_rr_gsb);
} else {
VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
module_manager,
grids, switches,
switches,
L_device_rr_gsb);
}
}
@ -452,7 +451,6 @@ void print_pnr_sdc(const SdcOption& sdc_options,
if (true == compact_routing_hierarchy) {
print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
module_manager,
grids,
switches,
L_device_rr_gsb);
} else {
@ -460,7 +458,6 @@ void print_pnr_sdc(const SdcOption& sdc_options,
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
module_manager,
L_device_rr_gsb,
grids,
switches);
}
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h
View File

@ -12,7 +12,6 @@
void print_pnr_sdc(const SdcOption& sdc_options,
const float& critical_path_delay,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& switches,
const DeviceRRGSB& L_device_rr_gsb,
const ModuleManager& module_manager,

3
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp
View File

@ -12,7 +12,6 @@
*******************************************************************/
void fpga_sdc_generator(const SdcOption& sdc_options,
const float& critical_path_delay,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<t_logical_block>& L_logical_blocks,
@ -32,7 +31,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options,
if (true == sdc_options.generate_sdc_pnr()) {
print_pnr_sdc(sdc_options, critical_path_delay,
grids, rr_switches, L_device_rr_gsb,
rr_switches, L_device_rr_gsb,
module_manager, mux_lib,
circuit_lib, global_ports,
compact_routing_hierarchy);

1
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h
View File

@ -9,7 +9,6 @@
void fpga_sdc_generator(const SdcOption& sdc_options,
const float& critical_path_delay,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<t_logical_block>& L_logical_blocks,

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c
View File

@ -171,7 +171,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
/* TODO: the critical path delay unit should be explicit! */
fpga_sdc_generator(sdc_options,
Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9,
grids, rr_switches, device_rr_gsb,
rr_switches, device_rr_gsb,
L_logical_blocks, device_size, grids, L_blocks,
module_manager, mux_lib,
Arch.spice->circuit_lib, global_ports,

4
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp
View File

@ -109,12 +109,12 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib,
arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids,
arch.sram_inf.verilog_sram_inf_orgz->type, sram_model,
vpr_setup.RoutingArch, rr_switches);
} else {
VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib,
arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids,
arch.sram_inf.verilog_sram_inf_orgz->type, sram_model,
vpr_setup.RoutingArch, rr_switches);
}

5
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp
View File

@ -62,7 +62,6 @@ ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_mana
ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const e_side& input_side,
t_rr_node* input_rr_node) {
/* Deposit an invalid value */
@ -108,7 +107,6 @@ ModulePortId find_switch_block_module_input_port(const ModuleManager& module_man
std::vector<ModulePortId> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_rr_node*>& input_rr_nodes) {
std::vector<ModulePortId> input_ports;
@ -121,7 +119,7 @@ std::vector<ModulePortId> find_switch_block_module_input_ports(const ModuleManag
VTR_ASSERT(NUM_SIDES != input_pin_side);
VTR_ASSERT(-1 != index);
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, input_rr_node));
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, input_pin_side, input_rr_node));
}
return input_ports;
@ -169,7 +167,6 @@ ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
t_rr_node* src_rr_node) {
/* Ensure the src_rr_node is an input pin of a CLB */

3
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h
View File

@ -17,14 +17,12 @@ ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_mana
ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const e_side& input_side,
t_rr_node* input_rr_node);
std::vector<ModulePortId> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_rr_node*>& input_rr_nodes);
ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager,
@ -36,7 +34,6 @@ ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGSB& rr_gsb,
const std::vector<std::vector<t_grid_tile>>& grids,
t_rr_node* src_rr_node);
std::vector<ModulePortId> find_connection_block_module_input_ports(const ModuleManager& module_manager,

46
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp
View File

@ -42,7 +42,6 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
const e_side& chan_side,
t_rr_node* cur_rr_node,
t_rr_node* drive_rr_node,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
/* Find the name of output port */
ModulePortId output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT);
@ -77,7 +76,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
exit(1);
}
/* Find the name of input port */
ModulePortId input_port_id = find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, drive_rr_node);
ModulePortId input_port_id = find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, input_pin_side, drive_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(sb_module, input_port_id);
@ -102,7 +101,6 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_side& chan_side,
const size_t& chan_node_id,
@ -136,7 +134,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name);
/* Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<ModulePortId> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_gsb, grids, drive_rr_nodes);
std::vector<ModulePortId> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_gsb, drive_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true);
@ -210,7 +208,6 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_side& chan_side,
const size_t& chan_node_id,
@ -235,20 +232,19 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
/* Print a special direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
rr_gsb, chan_side, cur_rr_node,
cur_rr_node, grids,
cur_rr_node,
input_port_to_module_nets);
} else if (1 == drive_rr_nodes.size()) {
/* Print a direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
rr_gsb, chan_side, cur_rr_node,
drive_rr_nodes[DEFAULT_SWITCH_ID],
grids,
input_port_to_module_nets);
} else if (1 < drive_rr_nodes.size()) {
/* Print the multiplexer, fan_in >= 2 */
build_switch_block_mux_module(module_manager,
sb_module, rr_gsb, circuit_lib,
grids, rr_switches, chan_side, chan_node_id, cur_rr_node,
rr_switches, chan_side, chan_node_id, cur_rr_node,
drive_rr_nodes,
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
input_port_to_module_nets);
@ -323,7 +319,6 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
static
void build_switch_block_module(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -392,7 +387,7 @@ void build_switch_block_module(ModuleManager& module_manager,
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
build_switch_block_interc_modules(module_manager,
sb_module, rr_gsb,
circuit_lib, grids, rr_switches,
circuit_lib, rr_switches,
side_manager.get_side(),
itrack,
input_port_to_module_nets);
@ -441,7 +436,6 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<std::vector<t_grid_tile>>& grids,
t_rr_node* src_rr_node,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
/* Ensure we have only one 1 driver node */
@ -464,7 +458,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
ModulePortId input_port_id = find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, drive_rr_node);
/* Create port description for input pin of a CLB */
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, src_rr_node);
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, src_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
@ -490,7 +484,6 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_side& cb_ipin_side,
const size_t& ipin_index,
@ -557,7 +550,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, cur_rr_node);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, cur_rr_node);
BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id);
/* Check port size should match */
@ -607,7 +600,6 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_side& cb_ipin_side,
const size_t& ipin_index,
@ -617,13 +609,13 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
return; /* This port has no driver, skip it */
} else if (1 == src_rr_node->fan_in) {
/* Print a direct connection */
build_connection_block_module_short_interc(module_manager, cb_module, rr_gsb, cb_type, grids, src_rr_node, input_port_to_module_nets);
build_connection_block_module_short_interc(module_manager, cb_module, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
} else if (1 < src_rr_node->fan_in) {
/* Print the multiplexer, fan_in >= 2 */
build_connection_block_mux_module(module_manager,
cb_module, rr_gsb, cb_type,
circuit_lib, grids, rr_switches,
circuit_lib, rr_switches,
cb_ipin_side, ipin_index,
input_port_to_module_nets);
} /*Nothing should be done else*/
@ -686,7 +678,6 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
static
void build_connection_block_module(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -781,7 +772,7 @@ void build_connection_block_module(ModuleManager& module_manager,
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
build_connection_block_interc_modules(module_manager,
cb_module, rr_gsb, cb_type,
circuit_lib, grids, rr_switches,
circuit_lib, rr_switches,
cb_ipin_side, inode,
input_port_to_module_nets);
}
@ -829,7 +820,6 @@ static
void build_flatten_connection_block_modules(ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const CircuitLibrary& circuit_lib,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -849,7 +839,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager,
}
build_connection_block_module(module_manager,
circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
rr_gsb, cb_type);
}
@ -870,7 +860,6 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
const std::vector<std::vector<t_grid_tile>>& grids,
const t_det_routing_arch& routing_arch,
const std::vector<t_switch_inf>& rr_switches) {
/* Start time count */
@ -890,7 +879,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
build_switch_block_module(module_manager, circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
rr_gsb);
}
@ -898,13 +887,13 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
build_flatten_connection_block_modules(module_manager, L_device_rr_gsb,
circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
CHANX);
build_flatten_connection_block_modules(module_manager, L_device_rr_gsb,
circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
CHANY);
@ -933,7 +922,6 @@ void build_unique_routing_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
const std::vector<std::vector<t_grid_tile>>& grids,
const t_det_routing_arch& routing_arch,
const std::vector<t_switch_inf>& rr_switches) {
/* Start time count */
@ -949,7 +937,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb);
build_switch_block_module(module_manager, circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
unique_mirror);
}
@ -960,7 +948,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
unique_mirror, CHANX);
}
@ -971,7 +959,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
circuit_lib,
grids, rr_switches,
rr_switches,
sram_orgz_type, sram_model,
unique_mirror, CHANY);
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h
View File

@ -16,7 +16,6 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
const std::vector<std::vector<t_grid_tile>>& grids,
const t_det_routing_arch& routing_arch,
const std::vector<t_switch_inf>& rr_switches);
@ -25,7 +24,6 @@ void build_unique_routing_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
const std::vector<std::vector<t_grid_tile>>& grids,
const t_det_routing_arch& routing_arch,
const std::vector<t_switch_inf>& rr_switches);