[core] fixed critical bugs in renaming modules

This commit is contained in:
tangxifan 2023-09-23 11:51:31 -07:00
parent c3443a288c
commit 860cfd53c6
3 changed files with 57 additions and 10 deletions

View File

@ -361,16 +361,23 @@ int rename_modules_template(T& openfpga_ctx, const Command& cmd,
std::string file_name = cmd_context.option_value(cmd, opt_file);
if (CMD_EXEC_SUCCESS !=
read_xml_module_name_map(file_name.c_str(),
openfpga_ctx.mutable_module_name_map())) {
int status = CMD_EXEC_SUCCESS;
ModuleNameMap user_module_name_map;
status = read_xml_module_name_map(file_name.c_str(), user_module_name_map);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* Write hierarchy to a file */
return rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
openfpga_ctx.module_name_map(),
cmd_context.option_enable(cmd, opt_verbose));
/* Apply renaming on the user version */
status = rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
user_module_name_map,
cmd_context.option_enable(cmd, opt_verbose));
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* Update the internal version of module name map based on users' version */
return update_module_name_map_with_user_version(openfpga_ctx.mutable_module_name_map(), user_module_name_map, cmd_context.option_enable(cmd, opt_verbose));
}
/********************************************************************

View File

@ -98,11 +98,17 @@ int rename_fabric_modules(ModuleManager& module_manager,
int status = CMD_EXEC_SUCCESS;
size_t cnt = 0;
for (ModuleId curr_module : module_manager.modules()) {
std::string curr_module_name = module_manager.module_name(curr_module);
/* Error out if the new name does not exist ! */
if (!module_name_map.name_exist(curr_module_name)) {
VTR_LOG_ERROR("The built-in module name '%s' does not exist! Abort renaming...\n", curr_module_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
std::string new_name =
module_name_map.name(module_manager.module_name(curr_module));
if (new_name != module_manager.module_name(curr_module)) {
module_name_map.name(curr_module_name);
if (new_name != curr_module_name) {
VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n",
module_manager.module_name(curr_module).c_str(),
curr_module_name.c_str(),
new_name.c_str());
module_manager.set_module_name(curr_module, new_name);
}
@ -112,4 +118,34 @@ int rename_fabric_modules(ModuleManager& module_manager,
return status;
}
/** @brief The module name map kept in openfpga context always has a built-in name with coordinates.
* while users apply renaming or other internal renaming is applied, e.g., through option '--name_module_using_index', the module name in the module graph can be changed. So in the user's version, the built-in name may become index or anything else.
* We have to keep the built-in name consistent (use coordinates, otherwise other engines may not work, which rely on this convention) while the given name should follow the users' definition. So we need an update here
* For example:
* the current module name map is 'tile_1__1_' -> 'tile_4_'
* the user's module name map is 'tile_4_' -> 'tile_big'
* The resulting module name map is 'tile_1__1_' -> 'tile_big'
*/
int update_module_name_map_with_user_version(ModuleNameMap& curr_module_name_map,
const ModuleNameMap& user_module_name_map,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
size_t cnt = 0;
for (std::string user_tag : user_module_name_map.tags()) {
if (!curr_module_name_map.tag_exist(user_tag)) {
VTR_LOG_ERROR("The built-in module name '%s' given by user does not exist in current module name map! Abort updating...\n", user_tag.c_str());
return CMD_EXEC_FATAL_ERROR;
}
std::string built_in_tag = curr_module_name_map.tag(user_tag);
curr_module_name_map.set_tag_to_name_pair(built_in_tag, user_module_name_map.name(user_tag));
VTR_LOGV(verbose, "Now module built-in name '%s' is pointed to its new name '%s' (old name '%s' is deleted)\n",
built_in_tag.c_str(),
user_module_name_map.name(user_tag).c_str(),
user_tag.c_str());
cnt++;
}
VTR_LOGV(verbose, "Update %lu built-in-to-name pairs\n", cnt);
return status;
}
} /* end namespace openfpga */

View File

@ -29,6 +29,10 @@ int rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose);
int update_module_name_map_with_user_version(ModuleNameMap& curr_module_name_map,
const ModuleNameMap& user_module_name_map,
const bool& verbose);
} /* end namespace openfpga */
#endif