[core] syntax

libs/libarchopenfpga/src/bitstream_setting_fwd.h

@@ -14,6 +14,7 @@
 #include "vtr_strong_id.h"
 
 struct bitstream_pb_type_setting_id_tag;
+struct bitstream_default_mode_setting_id_tag;
 struct bitstream_interconnect_setting_id_tag;
 struct overwrite_bitstream_id_tag;
 

libs/libarchopenfpga/src/write_xml_bitstream_setting.cpp

@@ -47,6 +47,40 @@ static std::string generate_bitstream_setting_pb_type_hierarchy_name(
   return hie_name;
 }
 
+/********************************************************************
+ * Generate the full hierarchy name for a pb_type in bitstream setting
+ *******************************************************************/
+static std::string generate_bitstream_setting_pb_type_hierarchy_name(
+  const openfpga::BitstreamSetting& bitstream_setting,
+  const BitstreamDefaultModeSettingId& bitstream_pb_type_setting_id) {
+  /* Iterate over the parent_pb_type and modes names, they should well match */
+  VTR_ASSERT_SAFE(
+    bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
+      .size() ==
+    bitstream_setting.default_mode_parent_mode_names(bitstream_pb_type_setting_id).size());
+
+  std::string hie_name;
+
+  for (size_t i = 0;
+       i < bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
+             .size();
+       ++i) {
+    hie_name +=
+      bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)[i];
+    hie_name += std::string("[");
+    hie_name +=
+      bitstream_setting.default_mode_parent_mode_names(bitstream_pb_type_setting_id)[i];
+    hie_name += std::string("]");
+    hie_name += std::string(".");
+  }
+
+  /* Add the leaf pb_type */
+  hie_name += bitstream_setting.default_mode_pb_type_name(bitstream_pb_type_setting_id);
+
+  return hie_name;
+}
+
+
 /********************************************************************
  * Generate the full hierarchy name for an interconnect in bitstream setting
  *******************************************************************/
@@ -121,7 +155,7 @@ static void write_xml_bitstream_pb_type_setting(
 /********************************************************************
  * A writer to output a bitstream pb_type setting to XML format
  *******************************************************************/
-static void write_xml_bitstream_pb_type_setting(
+static void write_xml_bitstream_default_mode_setting(
   std::fstream& fp, const char* fname,
   const openfpga::BitstreamSetting& bitstream_setting,
   const BitstreamDefaultModeSettingId& bitstream_default_mode_setting_id) {
@@ -139,7 +173,7 @@ static void write_xml_bitstream_pb_type_setting(
 
   write_xml_attribute(
     fp, "mode_bits",
-    bitstream_setting.default_mode_bits(bitstream_default_mode_setting_id)
+    bitstream_setting.default_mode_bits_to_string(bitstream_default_mode_setting_id)
       .c_str());
   fp << "/>"
      << "\n";

libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp

@@ -6,7 +6,7 @@
 # Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
 # md5sum of input file: 1db9d740309076fa51f61413bae1e072
 
-@0xdda3f3f93e497b0c;
+@0xe572df7b6c5621b7;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 

openfpga/src/annotation/annotate_bitstream_setting.cpp

@@ -182,7 +182,7 @@ static int annotate_bitstream_default_mode_setting(
           "Mismatches in length of default mode bits for a pb_type '%s' which is defined in bitstream setting ('%s') "
           "from OpenFPGA architecture description ('%s')\n",
           target_pb_type_names[0].c_str(), bitstream_setting.default_mode_bits_to_string(bitstream_default_mode_setting_id).c_str(),
-          vpr_device_annotation.pb_type_mode_bits_to_string(target_pb_type));
+          vpr_device_annotation.pb_type_mode_bits_to_string(target_pb_type).c_str());
         return CMD_EXEC_FATAL_ERROR;
       }
       vpr_device_annotation.add_pb_type_mode_bits(