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[Tool] Bug fix in the top testbench switch due to fast configuration

This commit is contained in:
tangxifan 2021-06-08 21:32:26 -06:00
parent 8db19c7af9
commit 85679c0fe2
1 changed files with 14 additions and 8 deletions
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10
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -2604,10 +2604,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Identify if we can apply fast configuration */
bool apply_fast_configuration = fast_configuration && is_fast_configuration_applicable(global_ports);
bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
bool bit_value_to_skip = false;
if (true == apply_fast_configuration) {
bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
global_ports,
bitstream_manager,
fabric_bitstream);
}
/* Start of testbench */
print_verilog_top_testbench_ports(fp, module_manager, top_module,
@ -2857,10 +2860,13 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
/* Identify if we can apply fast configuration */
bool apply_fast_configuration = fast_configuration && is_fast_configuration_applicable(global_ports);
bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
bool bit_value_to_skip = false;
if (true == apply_fast_configuration) {
bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
global_ports,
bitstream_manager,
fabric_bitstream);
}
/* Start of testbench */
print_verilog_top_testbench_ports(fp, module_manager, top_module,