diff --git a/README.md b/README.md index 52bde8429..1596dad69 100644 --- a/README.md +++ b/README.md @@ -24,9 +24,9 @@ You can find in the folder **./examples**. This will help you get in touch with In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base. -Example 1 shows a very basic design with only 4 inputs on the LUTs and 1 Basic Element in the CLBs. It implements an inverter and allows the user to see the very core of the .xml file. - - +Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file. + +Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added. diff --git a/examples/Examples_README.md b/examples/Examples_README.md new file mode 100644 index 000000000..63ac1b861 --- /dev/null +++ b/examples/Examples_README.md @@ -0,0 +1,67 @@ +# Examples_README + +## Example_1 + +The goal of this example is just to make a first step into the software. The .blif contains only an inverter. +The .xml is currently on which means that the size depends on the .blif. Since the .blif is +almost empty, only 1 CLB will be generated. + +![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_1.png "Example_1_FPGA") + + Schematic of the FPGA generated during example_1. + +The CLB integrates a 4-inputs LUT, a FF and a MUX. + +###**Things to understand in this example** + +Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures. + +```xml + + + ... add models such as the io pads. + + + ... all tech and spice parameters are defined here. + + ... define the Basic Elements of the architecture and the modules that cannot be generated (i.e. the Flip-Flop) but need to be called. + + + + ... complex blocks + + ... here we define the hierarchy of the primitive blocks and interconnect them together + + ... defines the primitive block + + + ... + + + + +``` + + +## Example_2 + +Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout. +In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry. +There is a feedbeck-loop from the output of the slices to the input MUXs + +![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_2_the_CLB_.png "Example_2_CLB") + + +###**Things to understand in this example** +```xml + + + + + + +``` + + + + diff --git a/examples/example_1.blif b/examples/example_1.blif index 13eee8a49..b696e7312 100644 --- a/examples/example_1.blif +++ b/examples/example_1.blif @@ -1,7 +1,7 @@ # Baudouin Chauviere University of Utah 30 September 2018 # Benchmark doing an inverter -.model s298.bench +.model inverter.bench .inputs I0 clk .outputs Q0 diff --git a/examples/example_2.blif b/examples/example_2.blif new file mode 100644 index 000000000..aeb37025b --- /dev/null +++ b/examples/example_2.blif @@ -0,0 +1,13 @@ +# Baudouin Chauviere University of Utah 30 September 2018 +# Benchmark doing an inverter + +.model example_2.bench +.inputs I0 clk +.outputs Q0 + +.latch n0 Q0 re clk 0 + +.names I0 n0 +0 1 + +.end \ No newline at end of file diff --git a/examples/example_2.sh b/examples/example_2.sh new file mode 100755 index 000000000..403736f7d --- /dev/null +++ b/examples/example_2.sh @@ -0,0 +1,9 @@ +#!/bin/sh +# Example of how to run vpr + +# Pack, place, and route a heterogeneous FPGA +# Packing uses the AAPack algorithm +../vpr7_x2p/vpr/vpr ./example_2.xml ./example_2.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test + + + diff --git a/examples/example_2.xml b/examples/example_2.xml new file mode 100644 index 000000000..c5b479a56 --- /dev/null +++ b/examples/example_2.xml @@ -0,0 +1,368 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/examples/figures/example_1.png b/examples/figures/example_1.png new file mode 100644 index 000000000..6bd678e2e Binary files /dev/null and b/examples/figures/example_1.png differ diff --git a/examples/figures/example_2_3x3.png b/examples/figures/example_2_3x3.png new file mode 100644 index 000000000..ee31c74e9 Binary files /dev/null and b/examples/figures/example_2_3x3.png differ diff --git a/examples/figures/example_2_the_CLB.png b/examples/figures/example_2_the_CLB.png new file mode 100644 index 000000000..d17fb92ea Binary files /dev/null and b/examples/figures/example_2_the_CLB.png differ