riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] code format

This commit is contained in:
tangxifan 2024-07-30 12:56:03 -07:00
parent f9f9aab7d9
commit 853883cd36
2 changed files with 12 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -418,7 +418,8 @@ static void try_find_and_add_clock_track2ipin_node(
const ClockTreePinId& clk_pin, const bool& verbose) { const ClockTreePinId& clk_pin, const bool& verbose) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
VTR_LOGV(verbose, "Getting type of grid at (x=%d, y=%d)\n", grid_coord.x(), grid_coord.y()); VTR_LOGV(verbose, "Getting type of grid at (x=%d, y=%d)\n", grid_coord.x(),
grid_coord.y());
for (std::string tap_pin_name : for (std::string tap_pin_name :
clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) {
VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str()); VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str());

23
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1157,11 +1157,9 @@ static void organize_top_module_tile_based_memory_modules(
********************************************************************/ ********************************************************************/
static ModulePinInfo find_tile_module_chan_port( static ModulePinInfo find_tile_module_chan_port(
const ModuleManager& module_manager, const ModuleId& tile_module, const ModuleManager& module_manager, const ModuleId& tile_module,
const vtr::Point<size_t>& cb_coord_in_tile, const vtr::Point<size_t>& cb_coord_in_tile, const size_t& cb_idx_in_tile,
const size_t& cb_idx_in_tile, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type,
const RRGraphView& rr_graph, const RRNodeId& chan_rr_node, const bool& name_module_using_index) {
const RRGSB& rr_gsb, const t_rr_type& cb_type, const RRNodeId& chan_rr_node,
const bool& name_module_using_index) {
ModulePinInfo input_port_info; ModulePinInfo input_port_info;
/* Generate the input port object */ /* Generate the input port object */
switch (rr_graph.node_type(chan_rr_node)) { switch (rr_graph.node_type(chan_rr_node)) {
@ -1173,14 +1171,15 @@ static ModulePinInfo find_tile_module_chan_port(
/* Create a port description for the middle output */ /* Create a port description for the middle output */
std::string input_port_name = generate_cb_module_track_port_name( std::string input_port_name = generate_cb_module_track_port_name(
cb_type, IN_PORT, 0 == chan_node_track_id % 2); cb_type, IN_PORT, 0 == chan_node_track_id % 2);
std::string cb_instance_name_in_tile = generate_connection_block_module_name(cb_type, cb_coord_in_tile); std::string cb_instance_name_in_tile =
generate_connection_block_module_name(cb_type, cb_coord_in_tile);
if (name_module_using_index) { if (name_module_using_index) {
cb_instance_name_in_tile = cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(cb_type, cb_idx_in_tile); generate_connection_block_module_name_using_index(cb_type,
cb_idx_in_tile);
} }
std::string tile_input_port_name = generate_tile_module_port_name( std::string tile_input_port_name = generate_tile_module_port_name(
cb_instance_name_in_tile, cb_instance_name_in_tile, input_port_name);
input_port_name);
/* Must find a valid port id in the Switch Block module */ /* Must find a valid port id in the Switch Block module */
input_port_info.first = input_port_info.first =
module_manager.find_module_port(tile_module, tile_input_port_name); module_manager.find_module_port(tile_module, tile_input_port_name);
@ -1278,10 +1277,8 @@ static int build_top_module_global_net_from_tile_clock_arch_tree(
unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile]; unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile];
ModulePinInfo des_pin_info = find_tile_module_chan_port( ModulePinInfo des_pin_info = find_tile_module_chan_port(
module_manager, tile_module, cb_coord_in_unique_fabric_tile, module_manager, tile_module, cb_coord_in_unique_fabric_tile,
cb_idx_in_curr_fabric_tile, cb_idx_in_curr_fabric_tile, rr_graph, rr_gsb, entry_track_type,
rr_graph, entry_rr_node, name_module_using_index);
rr_gsb, entry_track_type, entry_rr_node,
name_module_using_index);
/* Configure the net sink */ /* Configure the net sink */
BasicPort sink_port = BasicPort sink_port =