diff --git a/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints.xml b/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints.xml
new file mode 100644
index 000000000..88ccaefa5
--- /dev/null
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints.xml
@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of the FPGA fabric
+       - the clk1 signal to the clk[1] port of the FPGA fabric
+    -->
+  <set_io pin="clk[0]" net="clk"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
index 9540535b0..89622f147 100644
--- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
@@ -37,7 +38,7 @@ bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_
 bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
 bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
-#bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench0_top = counter
 bench1_top = counter