[test] fixed the bug in adder mapping

openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys

@@ -41,7 +41,7 @@ clean
 abc -lut ${LUT_SIZE}
 
 # Check
-synth -run check
+#synth -run check
 
 # Clean and output blif
 opt_clean -purge

openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v

@@ -3,13 +3,12 @@
 //---------------------------------------
 (* abc9_box, lib_whitebox *)
 module adder(
-	input cin,
+    output sumout,
+    output cout,
     input a,
     input b,
-	output cout,
-	output sumout );
-
-
+    input cin
+);
     assign sumout = a ^ b ^ cin;
     assign cout = (a & b) | ((a | b) & cin);
 

openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v

@@ -3,7 +3,7 @@
 // Many thanks to F4PGA for their contribution
 
 (* techmap_celltype = "$alu" *)
-module _openfpga_alu (A, B, CI, BI, X, Y, CO);
+module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
 
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;

openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf

@@ -33,6 +33,7 @@ bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga
 bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
 bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 # Benchmark information
 bench0_top = adder_8