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[test] fixed the bug in adder mapping

This commit is contained in:
tangxifan 2023-06-20 17:09:31 -07:00
parent dba48fb171
commit 84edd41342
4 changed files with 11 additions and 11 deletions
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2
openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
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@ -41,7 +41,7 @@ clean
abc -lut ${LUT_SIZE} abc -lut ${LUT_SIZE}
# Check # Check
synth -run check #synth -run check
# Clean and output blif # Clean and output blif
opt_clean -purge opt_clean -purge

17
openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v
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@ -3,14 +3,13 @@
//--------------------------------------- //---------------------------------------
(* abc9_box, lib_whitebox *) (* abc9_box, lib_whitebox *)
module adder( module adder(
input cin, output sumout,
input a, output cout,
input b, input a,
output cout, input b,
output sumout ); input cin
);
assign sumout = a ^ b ^ cin;
assign sumout = a ^ b ^ cin; assign cout = (a & b) | ((a | b) & cin);
assign cout = (a & b) | ((a | b) & cin);
endmodule endmodule

2
openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
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@ -3,7 +3,7 @@
// Many thanks to F4PGA for their contribution // Many thanks to F4PGA for their contribution
(* techmap_celltype = "$alu" *) (* techmap_celltype = "$alu" *)
module _openfpga_alu (A, B, CI, BI, X, Y, CO); module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;

1
openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
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@ -33,6 +33,7 @@ bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga
bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
bench_read_verilog_options_common = -nolatches bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
# Benchmark information # Benchmark information
bench0_top = adder_8 bench0_top = adder_8