diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 009b834fe..26949ec29 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -96,7 +96,6 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      */
     std::string src_instance_name; 
     if (parent_module != src_module) {
-      src_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
       size_t instance_id = src_pb_graph_node->placement_index;
       if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) {  
@@ -126,7 +125,6 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      */
     std::string des_instance_name; 
     if (parent_module != des_module) {
-      des_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
       size_t instance_id = des_pb_graph_node->placement_index;
       if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) {  
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 014142fb1..90f20b2b7 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -52,6 +52,7 @@ write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here 
+write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie
 write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric