From 845436fa71ddf610c89a7cc0bacd3c53d4649e36 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 17 Nov 2020 14:34:54 -0700 Subject: [PATCH] [Test] Add sequential benchmark for global tile clock test case --- .../global_tile_ports/global_tile_clock/config/task.conf | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index 55f5a13d0..6267eda37 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml @@ -25,10 +25,14 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_ [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v [SYNTHESIS_PARAM] bench0_top = and2 bench0_chan_width = 300 +bench1_top = and2_latch +bench1_chan_width = 300 + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=