diff --git a/docs/source/conf.py b/docs/source/conf.py
index 0f442d9bd..03c1cdb47 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -185,6 +185,8 @@ texinfo_documents = [
 ]
 
 
+bibtex_bibfiles = ["z_reference.bib"]
+
 # -- Options for Epub output -------------------------------------------------
 
 # Bibliographic Dublin Core info.
diff --git a/docs/source/dev_manual/ci_cd_setup/index.rst b/docs/source/dev_manual/ci_cd_setup/index.rst
index 6d213c0ad..8d4802d82 100644
--- a/docs/source/dev_manual/ci_cd_setup/index.rst
+++ b/docs/source/dev_manual/ci_cd_setup/index.rst
@@ -105,4 +105,16 @@ Release Docker Images
 
     This is a bleeding-edge release from the current master branch of OpenFPGA.
     It is updated automatically whenever there is activity on the master branch.
-    Due to high development activity, we recommend the user to use the bleeding-edge version to get access to all new features and report an issue in case there are any bugs.
\ No newline at end of file
+    Due to high development activity, we recommend the user to use the bleeding-edge version to get access to all new features and report an issue in case there are any bugs.
+
+
+CI after cloning repository
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+If you clone the repository the CI setup will still function, except the based images are  still pullled from "lnis-uofu" repsitory and the master branch
+of cloned repo will not push final docker image to any repository .
+
+**In case you want to host your own copies of OpenFPGA base images** and final release create a githib secret variable with name  ``DOCKER_REPO`` and set it to ``true``. This will make ci script to download base images from your own repo pakcages, and upload final realse to the same.
+
+**If you don not want to use docker images based regression test** and like to compile all the bianries for each CI run. You can set ``IGNORE_DOCKER_TEST`` secrete variable to ``true``.
+
+.. note:: Once you add ``DOCKER_REPO`` variable, you need to genrerate base images. To do this trigger mannual workflow ``Build docker CI images``
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
index ed8f0134c..9bf8c440c 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
@@ -210,8 +210,8 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="A" lib_name="A" size="36"/>
-      <port type="input" prefix="B" lib_name="B" size="36"/>
+      <port type="input" prefix="A" lib_name="a" size="36"/>
+      <port type="input" prefix="B" lib_name="b" size="36"/>
       <port type="output" prefix="Y" lib_name="out" size="72"/>
       <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
       <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
index d1cf24921..9b23d0a9c 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
@@ -211,8 +211,8 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="A" lib_name="A" size="36"/>
-      <port type="input" prefix="B" lib_name="B" size="36"/>
+      <port type="input" prefix="A" lib_name="a" size="36"/>
+      <port type="input" prefix="B" lib_name="b" size="36"/>
       <port type="output" prefix="Y" lib_name="out" size="72"/>
       <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
       <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
index 9a7a27aa9..6e49dead4 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
@@ -198,9 +198,9 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" lib_name="A" size="36"/>
-      <port type="input" prefix="b" lib_name="B" size="36"/>
-      <port type="output" prefix="out" size="72"/>
+      <port type="input" prefix="a" lib_name="a" size="36"/>
+      <port type="input" prefix="b" lib_name="b" size="36"/>
+      <port type="output" prefix="out" lib_name="out" size="72"/>
       <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
       <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index f7a8742b9..207e198d3 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -198,9 +198,9 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" lib_name="A" size="36"/>
-      <port type="input" prefix="b" lib_name="B" size="36"/>
-      <port type="output" prefix="out" size="72"/>
+      <port type="input" prefix="a" lib_name="a" size="36"/>
+      <port type="input" prefix="b" lib_name="b" size="36"/>
+      <port type="output" prefix="out" lib_name="out" size="72"/>
       <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
       <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>