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[Architecture] Update cell ports for native SRAM cell

This commit is contained in:
tangxifan 2020-09-24 10:31:31 -06:00
parent e454467799
commit 83971bba41
2 changed files with 24 additions and 25 deletions
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34
openfpga_flow/VerilogNetlists/sram.v
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@ -1,31 +1,31 @@
//----------------------------------------------------- //-----------------------------------------------------
// Design Name : sram_blwl // Design Name : sram_blwl
// File Name : sram.v // File Name : sram.v
// Function : A SRAM cell is is accessible
// when wl is enabled
// Coder : Xifan TANG // Coder : Xifan TANG
//----------------------------------------------------- //-----------------------------------------------------
module sram_blwl(
input reset, // Word line control signal
input wl, // Word line control signal //-----------------------------------------------------
input bl, // Bit line control signal // Function : A SRAM cell with write enable
output out, // Data output //-----------------------------------------------------
output outb // Data output module SRAM(
input WE, // Word line control signal as write enable
input D, // Bit line control signal
output Q, // Data output
output QN // Data output
); );
//----- local variable need to be registered //----- local variable need to be registered
reg data; reg data;
//----- when wl is enabled, we can read in data from bl //----- when wl is enabled, we can read in data from bl
always @(bl or wl) always @(WE or D)
begin begin
if (1'b1 == reset) begin if ((1'b1 == D)&&(1'b1 == WE)) begin
data <= 1'b0;
end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
//----- Cases to program internal memory bit //----- Cases to program internal memory bit
//----- case 1: bl = 1, wl = 1, a -> 0 //----- case 1: bl = 1, wl = 1, a -> 0
data <= 1'b1; data <= 1'b1;
end else if ((1'b0 == bl)&&(1'b1 == wl)) begin end else if ((1'b0 == D)&&(1'b1 == WE)) begin
//----- case 2: bl = 0, wl = 1, a -> 0 //----- case 2: bl = 0, wl = 1, a -> 0
data <= 1'b0; data <= 1'b0;
end end
@ -33,11 +33,11 @@ output outb // Data output
`ifndef ENABLE_FORMAL_VERIFICATION `ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q // Wire q_reg to Q
assign out = data; assign Q = data;
assign outb = ~data; assign QN = ~data;
`else `else
assign out = 1'bZ; assign Q = 1'bZ;
assign outb = !out; assign QN = !out;
`endif `endif
endmodule endmodule

15
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
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@ -146,28 +146,27 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="sram_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="bl" prefix="bl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
<port type="output" prefix="outb" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram_blwl" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="SRAM" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="memory_bank" circuit_model_name="sram_blwl"/> <organization type="memory_bank" circuit_model_name="SRAM"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>