riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[engine] fixed a bug on mistakenly adding I/O child modules for direct connections

This commit is contained in:
tangxifan 2022-09-14 17:13:23 -07:00
parent 036933dc14
commit 8378ad4bf3
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -131,7 +131,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
/* Add a submodule of direct connection module to the top-level module */ /* Add a submodule of direct connection module to the top-level module */
size_t direct_instance_id = module_manager.num_instance(top_module, direct_module); size_t direct_instance_id = module_manager.num_instance(top_module, direct_module);
module_manager.add_child_module(top_module, direct_module); module_manager.add_child_module(top_module, direct_module, false);
/* Create the 1st module net */ /* Create the 1st module net */
ModuleNetId net_direct_src = module_manager.create_module_net(top_module); ModuleNetId net_direct_src = module_manager.create_module_net(top_module);