diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp index 170c7dfc5..320d1300e 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp @@ -10,7 +10,8 @@ RRClockSpatialLookup::RRClockSpatialLookup() {} RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, const ClockLevelId& lvl, const ClockTreePinId& pin, - const Direction& direction) const { + const Direction& direction, + const bool& verbose) const { size_t dir = size_t(direction); /* Pre-check: the x, y, side and ptc should be non negative numbers! * Otherwise, return an invalid id */ @@ -25,12 +26,12 @@ RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, * - Return an invalid id if any out-of-range is detected */ if (size_t(dir) >= rr_node_indices_.size()) { - VTR_LOG("Direction out of range\n"); + VTR_LOGV(verbose, "Direction out of range\n"); return RRNodeId::INVALID(); } if (size_t(x) >= rr_node_indices_[dir].dim_size(0)) { - VTR_LOG("X out of range\n"); + VTR_LOGV(verbose, "X out of range\n"); return RRNodeId::INVALID(); } @@ -40,18 +41,18 @@ RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, } if (size_t(tree) >= rr_node_indices_[dir][x][y].size()) { - VTR_LOG("Tree id out of range\n"); + VTR_LOGV(verbose, "Tree id out of range\n"); return RRNodeId::INVALID(); } if (size_t(lvl) == rr_node_indices_[dir][x][y][size_t(tree)].size()) { - VTR_LOG("Level id out of range\n"); + VTR_LOGV(verbose, "Level id out of range\n"); return RRNodeId::INVALID(); } if (size_t(pin) == rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) { - VTR_LOG("Pin id out of range\n"); + VTR_LOGV(verbose, "Pin id out of range\n"); return RRNodeId::INVALID(); } diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h index 650c3e368..01df8ab9f 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h @@ -58,7 +58,7 @@ class RRClockSpatialLookup { */ RRNodeId find_node(int x, int y, const ClockTreeId& tree, const ClockLevelId& lvl, const ClockTreePinId& pin, - const Direction& direction) const; + const Direction& direction, const bool& verbose) const; /* -- Mutators -- */ public: diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 737b78a08..5641a57aa 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -262,7 +262,7 @@ static std::vector find_clock_track2track_node( const RRClockSpatialLookup& clk_rr_lookup, const t_rr_type& chan_type, const vtr::Point& chan_coord, const ClockTreeId& clk_tree, const ClockLevelId& clk_lvl, const ClockTreePinId& clk_pin, - const Direction& direction) { + const Direction& direction, const bool& verbose) { std::vector des_nodes; /* Straight connection */ @@ -285,7 +285,7 @@ static std::vector find_clock_track2track_node( } RRNodeId straight_des_node = clk_rr_lookup.find_node(straight_des_coord.x(), straight_des_coord.y(), - clk_tree, clk_lvl, clk_pin, direction); + clk_tree, clk_lvl, clk_pin, direction, verbose); if (rr_graph_view.valid_node(straight_des_node)) { VTR_ASSERT(chan_type == rr_graph_view.node_type(straight_des_node)); des_nodes.push_back(straight_des_node); @@ -344,7 +344,7 @@ static std::vector find_clock_track2track_node( } RRNodeId left_des_node = clk_rr_lookup.find_node(left_des_coord.x(), left_des_coord.y(), clk_tree, - next_clk_lvl, clk_pin, left_direction); + next_clk_lvl, clk_pin, left_direction, verbose); if (rr_graph_view.valid_node(left_des_node)) { VTR_ASSERT(left_des_chan_type == rr_graph_view.node_type(left_des_node)); des_nodes.push_back(left_des_node); @@ -396,7 +396,7 @@ static std::vector find_clock_track2track_node( } RRNodeId right_des_node = clk_rr_lookup.find_node(right_des_coord.x(), right_des_coord.y(), clk_tree, - next_clk_lvl, clk_pin, right_direction); + next_clk_lvl, clk_pin, right_direction, verbose); if (rr_graph_view.valid_node(right_des_node)) { VTR_ASSERT(right_des_chan_type == rr_graph_view.node_type(right_des_node)); des_nodes.push_back(right_des_node); @@ -535,7 +535,7 @@ static void add_rr_graph_block_clock_edges( /* find the driver clock node through lookup */ RRNodeId src_node = clk_rr_lookup.find_node(chan_coord.x(), chan_coord.y(), itree, ilvl, - ClockTreePinId(ipin), node_dir); + ClockTreePinId(ipin), node_dir, verbose); VTR_LOGV(verbose, "Try to find node '%lu' from clock node lookup (x='%lu' " "y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n", @@ -548,7 +548,7 @@ static void add_rr_graph_block_clock_edges( size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2track_node( rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type, - chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { + chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir, verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge( @@ -593,7 +593,7 @@ static void try_find_and_add_clock_opin2track_node( const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, - const ClockInternalDriverId& int_driver_id) { + const ClockInternalDriverId& int_driver_id, const bool& verbose) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : @@ -606,6 +606,7 @@ static void try_find_and_add_clock_opin2track_node( RRNodeId opin_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(opin_node)) { + VTR_LOGV(verbose, "Connected OPIN '%s' to clock network\n", tap_pin_name.c_str()); opin_nodes.push_back(opin_node); } } @@ -639,7 +640,8 @@ static std::vector find_clock_opin2track_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& sb_coord, const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, - const std::vector& int_driver_ids) { + const std::vector& int_driver_ids, + const bool& verbose) { std::vector opin_nodes; /* Find opins from * - Grid[x][y+1] on right and bottom sides @@ -663,7 +665,7 @@ static std::vector find_clock_opin2track_node( for (ClockInternalDriverId int_driver_id : int_driver_ids) { try_find_and_add_clock_opin2track_node( opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side, - clk_ntwk, clk_pin, int_driver_id); + clk_ntwk, clk_pin, int_driver_id, verbose); } } } @@ -704,7 +706,7 @@ static int add_rr_graph_opin2clk_edges( ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); + des_spine_level, ipin, des_spine_direction, verbose); /* Walk through each qualified OPIN, build edges */ vtr::Point src_coord = clk_ntwk.spine_switch_point(ispine, switch_point_id); @@ -713,7 +715,7 @@ static int add_rr_graph_opin2clk_edges( switch_point_id); for (RRNodeId src_node : find_clock_opin2track_node( grids, rr_graph_view, layer, src_coord, clk_ntwk, ipin, - int_driver_ids)) { + int_driver_ids, verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge( diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index a0e57bda5..0772b511f 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -110,10 +110,10 @@ static int route_clock_spine_switch_point( ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); + src_spine_level, ipin, src_spine_direction, verbose); RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); + des_spine_level, ipin, des_spine_direction, verbose); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); /* Internal drivers may appear at the switch point. Check if there are @@ -202,7 +202,7 @@ static int route_spine_taps( ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); + src_spine_level, ipin, src_spine_direction, verbose); for (RREdgeId edge : rr_graph.edge_range(src_node)) { RRNodeId des_node = rr_graph.edge_sink_node(edge); if (rr_graph.node_type(des_node) == IPIN) { @@ -391,10 +391,10 @@ static int rec_expand_and_route_clock_spine( ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, curr_pin, src_spine_direction); + src_spine_level, curr_pin, src_spine_direction, verbose); RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, curr_pin, des_spine_direction); + des_spine_level, curr_pin, des_spine_direction, verbose); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); VTR_LOGV(verbose, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 9e1f9b225..efb1919db 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1249,7 +1249,7 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( /* Find the routing resource node of the entry point */ RRNodeId entry_rr_node = rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree, - clk_ntwk.spine_level(spine), pin, entry_dir); + clk_ntwk.spine_level(spine), pin, entry_dir, false); /* Get the tile module and instance at the entry point */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 16b0823df..ab37d5363 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1284,7 +1284,7 @@ static int build_top_module_global_net_from_clock_arch_tree( /* Find the routing resource node of the entry point */ RRNodeId entry_rr_node = rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree, - clk_ntwk.spine_level(spine), pin, entry_dir); + clk_ntwk.spine_level(spine), pin, entry_dir, false); /* Get the connection block module and instance at the entry point */ vtr::Point entry_cb_coord(entry_point.x(), entry_point.y());