[test] adjust W
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=40
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openfpga_vpr_route_chan_width=60
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openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
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openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
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openfpga_route_clock_options=
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