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[Architecture] Bug fix in DFF Verilog HDL

This commit is contained in:
tangxifan 2020-09-24 14:53:21 -06:00
parent 3b42fe94d6
commit 81965e75f6
1 changed files with 1 additions and 1 deletions
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openfpga_flow/VerilogNetlists/dff.v
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@ -17,7 +17,7 @@ module DFF (
reg q_reg; reg q_reg;
//-------------Code Starts Here--------- //-------------Code Starts Here---------
always @ ( posedge CK) always @ (posedge CK) begin
q_reg <= D; q_reg <= D;
end end