From 813470d4599ddfcbe49b451e0ed4296537625bea Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 3 Jun 2019 10:31:44 -0600 Subject: [PATCH] Test Cmake fix --- .travis.yml | 1 + vpr7_x2p/vpr/.regression_verilog.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 758757453..7a29d2cee 100644 --- a/.travis.yml +++ b/.travis.yml @@ -91,6 +91,7 @@ install: brew install cmake || brew upgrade cmake fi - cmake --version + - cd - - .travis/install.sh script: diff --git a/vpr7_x2p/vpr/.regression_verilog.sh b/vpr7_x2p/vpr/.regression_verilog.sh index 132b4bdb2..75962bf0c 100755 --- a/vpr7_x2p/vpr/.regression_verilog.sh +++ b/vpr7_x2p/vpr/.regression_verilog.sh @@ -37,7 +37,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname # Run VPR #valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl #--fpga_verilog_print_sdc_analysis --fpga_verilog_print_sdc_pnr --power --tech_properties /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis --fpga_verilog_print_sdc_pnr