From 812d8c950eb3864a4de620c45c6e9e85bd76bfee Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 8 Mar 2021 21:39:44 -0700
Subject: [PATCH] [Script] Update quicklogic's script to output correct verilog
 file name

---
 openfpga_flow/misc/qlf_yosys.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys
index e0b530564..587769941 100644
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@@ -4,4 +4,4 @@ ${READ_VERILOG_FILE}
 
 synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
 
-write_verilog -noattr -nohex ${OUTPUT_VERILOG}.v
+write_verilog -noattr -nohex ${OUTPUT_VERILOG}