diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
index 62220e535..ebd69fb73 100644
--- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf
+++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
@@ -50,8 +50,8 @@ yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif
 yosys_output=yosys_output.txt
 
 # ACE2 and intermidiate file
-activity_file=${PATH:TOP_MODULE}_ace_out.act
-ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif
+activity_file=${PATH:TOP_MODULE}.act
+ace_output_blif=${PATH:TOP_MODULE}.blif
 corrected_format_blif=${PATH:TOP_MODULE}.blif
 blackbox_blif=${PATH:TOP_MODULE}_bb.blif
 
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 1593d3f85..40575ad9c 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -634,6 +634,7 @@ def run_openfpga_shell():
     path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
     path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
     path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
+    path_variables["TECH_PROPERTIES"] = args.power_tech
     path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
         "_output_verilog.v"