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fixed errors

This commit is contained in:
ANDREW HARRIS POND 2021-07-01 16:40:03 -06:00
parent 006b54c4bc
commit 808821bb8c
1 changed files with 21 additions and 20 deletions
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5
openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
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@ -35,15 +35,16 @@ module reset_generator(
`ifdef VIVADO_SYNTHESIS
initial begin
pulse <= INITIAL_VALUE;
clkdiv_counter <= 0;
active_cycle_counter <= 0;
pulse <= INITIAL_VALUE;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk) begin
if (active_cycle_counter == ACTIVE_CYCLES) begin
pulse <= ~INITIAL_VALUE;
pulse <= ~pulse;
end else begin
active_cycle_counter <= active_cycle_counter + 1;
end