From 801055b007eab71d9113eaf4e5654e75ab74f375 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:47:02 -0600
Subject: [PATCH] [OpenFPGA Tool] Bug Fix on the tileable RRG for multi segment

---
 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index ad4944bb4..2cef83e5c 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -1211,7 +1211,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
         ipin_Fc_out.push_back(ipin_Fc);
         if (0 != ipin_Fc) { 
           skip_conn2track = false;
-          break;
+          continue;
         }
       }
 
@@ -1290,7 +1290,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
         opin_Fc_out.push_back(opin_Fc);
         if (0 != opin_Fc) { 
           skip_conn2track = false;
-          break;
+          continue;
         }
       }