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[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs

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tangxifan 2021-03-22 10:39:47 -06:00
parent cc10b10703
commit 7fd345a616
1 changed files with 3 additions and 0 deletions
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3
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
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@ -40,6 +40,9 @@ opt_clean
# Map multipliers # Map multipliers
# Inspired from synth_xilinx.cc # Inspired from synth_xilinx.cc
######################### #########################
# Avoid merging any registers into DSP, reserve memory port registers first
memory_dff
wreduce t:$mul
techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
select a:mul2dsp select a:mul2dsp
setattr -unset mul2dsp setattr -unset mul2dsp