From 6400605603000d18882123e8c9f8c983c68c7357 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 16:39:06 -0800
Subject: [PATCH 01/18] [benchmark] add clock divider

---
 .../micro_benchmark/clk_divider/clk_divider.v | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v b/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
new file mode 100644
index 000000000..c559f49d7
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
@@ -0,0 +1,28 @@
+/////////////////////////////////////////
+//  Functionality: A two-stage clock divider (Frequency is divided by 4)
+//                 This is to test the clock generated locally by a LUT/FF
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module clk_divider(clk_i, clk_o);
+
+input wire clk_i;
+output reg clk_o;
+
+reg int_clk;
+
+initial begin
+  clk_o <= 0;
+  int_clk <= 0;
+end
+
+always @(posedge clk_i) begin
+  int_clk <= ~int_clk;
+end
+
+always @(posedge int_clk) begin
+  clk_o <= ~clk_o;
+end
+
+endmodule

From 1353577351d0bc61b81ddc87d240b304c97fcf77 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 16:45:30 -0800
Subject: [PATCH 02/18] [test] added a new test to validate locally generated
 clocks

---
 .../config/pin_constraints_reset.xml          |  4 ++
 .../config/repack_design_constraints.xml      |  4 ++
 .../k4_series/k4n4_clk_gen/config/task.conf   | 43 +++++++++++++++++++
 3 files changed, 51 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
new file mode 100644
index 000000000..20a21d2cf
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
@@ -0,0 +1,4 @@
+<pin_constraints>
+  <!-- Intended to be dummy -->
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
new file mode 100644
index 000000000..06a125111
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
@@ -0,0 +1,4 @@
+<repack_design_constraints>
+  <!-- Intended to be dummy -->
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
new file mode 100644
index 000000000..1cf981d22
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -0,0 +1,43 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = clk_divider
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From a06ee30ca0d1887a50c49dedbf602905cb0088c2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 19:35:00 -0800
Subject: [PATCH 03/18] [arch] added a new vpr arch where clock can be
 generated by internal logics

---
 ...ac_N4_tileable_fracff_localClkGen_40nm.xml | 631 ++++++++++++++++++
 1 file changed, 631 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
new file mode 100644
index 000000000..6822f473a
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
@@ -0,0 +1,631 @@
+<?xml version="1.0"?>
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Authors: Xifan Tang
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="dff">
+      <input_ports>
+        <port name="D" clock="C"/>
+        <port name="C" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="C"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="dffr">
+      <input_ports>
+        <port name="D" clock="C"/>
+        <port name="R" clock="C"/>
+        <port name="C" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="C"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="dffrn">
+      <input_ports>
+        <port name="D" clock="C"/>
+        <port name="RN" clock="C"/>
+        <port name="C" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="C"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" area="0">
+      <sub_tile name="io" capacity="8">
+        <equivalent_sites>
+          <site pb_type="io"/>
+        </equivalent_sites>
+        <input name="outpad" num_pins="1"/>
+        <output name="inpad" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+        <pinlocations pattern="custom">
+          <loc side="left">io.outpad io.inpad</loc>
+          <loc side="top">io.outpad io.inpad</loc>
+          <loc side="right">io.outpad io.inpad</loc>
+          <loc side="bottom">io.outpad io.inpad</loc>
+        </pinlocations>
+      </sub_tile>
+    </tile>
+    <tile name="clb" area="53894">
+      <sub_tile name="clb">
+        <equivalent_sites>
+          <site pb_type="clb"/>
+        </equivalent_sites>
+        <input name="I" num_pins="12" equivalent="full"/>
+        <input name="reset" num_pins="1" is_non_clock_global="true"/>
+        <output name="O" num_pins="8" equivalent="none"/>
+        <clock name="clk" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
+        </fc>
+        <pinlocations pattern="spread"/>
+      </sub_tile>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <fixed_layout name="48x48" width="50" height="50">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disable_packing="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="reset" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="reset" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disable_packing="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="reset" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
+              <input name="D" num_pins="1" port_class="D"/>
+              <input name="R" num_pins="1"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="C" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="C"/>
+              <T_setup value="66e-12" port="ff.R" clock="C"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].C"/>
+              <complete name="direct4" input="fabric.reset" output="ff[1:0].R"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+            <direct name="direct4" input="fle.reset" output="fabric.reset"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="reset" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <input name="reset" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" num_pb="1">
+                <input name="D" num_pins="1"/>
+                <input name="R" num_pins="1"/>
+                <output name="Q" num_pins="1"/>
+                <clock name="C" num_pins="1"/>
+                <mode name="latch">
+                  <pb_type name="latch" blif_model=".latch" num_pb="1">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="latch.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="ff.D" output="latch.D"/>
+                    <direct name="direct2" input="ff.C" output="latch.clk"/>
+                    <direct name="direct3" input="latch.Q" output="ff.Q"/>
+                  </interconnect>
+                </mode>
+                <mode name="dff">
+                  <pb_type name="dff" blif_model=".subckt dff" num_pb="1">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="C" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="dff.D" clock="C"/>
+                    <T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="ff.D" output="dff.D"/>
+                    <direct name="direct2" input="ff.C" output="dff.C"/>
+                    <direct name="direct3" input="dff.Q" output="ff.Q"/>
+                  </interconnect>
+                </mode>
+                <mode name="dffr">
+                  <pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <input name="R" num_pins="1"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="C" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="dffr.D" clock="C"/>
+                    <T_setup value="66e-12" port="dffr.R" clock="C"/>
+                    <T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="ff.D" output="dffr.D"/>
+                    <direct name="direct2" input="ff.C" output="dffr.C"/>
+                    <direct name="direct3" input="ff.R" output="dffr.R"/>
+                    <direct name="direct4" input="dffr.Q" output="ff.Q"/>
+                  </interconnect>
+                </mode>
+                <mode name="dffrn">
+                  <pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <input name="RN" num_pins="1"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="C" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="dffrn.D" clock="C"/>
+                    <T_setup value="66e-12" port="dffrn.RN" clock="C"/>
+                    <T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="ff.D" output="dffrn.D"/>
+                    <direct name="direct2" input="ff.C" output="dffrn.C"/>
+                    <direct name="direct3" input="ff.R" output="dffrn.RN"/>
+                    <direct name="direct4" input="dffrn.Q" output="ff.Q"/>
+                  </interconnect>
+                </mode>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].C"/>
+                <direct name="direct4" input="ble3.reset" output="ff[0:0].R"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+              <complete name="complete2" input="lut3inter.reset" output="ble3[1:0].reset"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+            <direct name="direct4" input="fle.reset" output="lut3inter.reset"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="reset" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define the flip-flop -->
+            <pb_type name="ff" num_pb="1">
+              <input name="D" num_pins="1"/>
+              <input name="R" num_pins="1"/>
+              <output name="Q" num_pins="1"/>
+              <clock name="C" num_pins="1"/>
+              <mode name="latch">
+                <pb_type name="latch" blif_model=".latch" num_pb="1">
+                  <input name="D" num_pins="1" port_class="D"/>
+                  <output name="Q" num_pins="1" port_class="Q"/>
+                  <clock name="clk" num_pins="1" port_class="clock"/>
+                  <T_setup value="66e-12" port="latch.D" clock="clk"/>
+                  <T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ff.D" output="latch.D"/>
+                  <direct name="direct2" input="ff.C" output="latch.clk"/>
+                  <direct name="direct3" input="latch.Q" output="ff.Q"/>
+                </interconnect>
+              </mode>
+              <mode name="dff">
+                <pb_type name="dff" blif_model=".subckt dff" num_pb="1">
+                  <input name="D" num_pins="1" port_class="D"/>
+                  <output name="Q" num_pins="1" port_class="Q"/>
+                  <clock name="C" num_pins="1" port_class="clock"/>
+                  <T_setup value="66e-12" port="dff.D" clock="C"/>
+                  <T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ff.D" output="dff.D"/>
+                  <direct name="direct2" input="ff.C" output="dff.C"/>
+                  <direct name="direct3" input="dff.Q" output="ff.Q"/>
+                </interconnect>
+              </mode>
+              <mode name="dffr">
+                <pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
+                  <input name="D" num_pins="1" port_class="D"/>
+                  <input name="R" num_pins="1"/>
+                  <output name="Q" num_pins="1" port_class="Q"/>
+                  <clock name="C" num_pins="1" port_class="clock"/>
+                  <T_setup value="66e-12" port="dffr.D" clock="C"/>
+                  <T_setup value="66e-12" port="dffr.R" clock="C"/>
+                  <T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ff.D" output="dffr.D"/>
+                  <direct name="direct2" input="ff.C" output="dffr.C"/>
+                  <direct name="direct3" input="ff.R" output="dffr.R"/>
+                  <direct name="direct4" input="dffr.Q" output="ff.Q"/>
+                </interconnect>
+              </mode>
+              <mode name="dffrn">
+                <pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
+                  <input name="D" num_pins="1" port_class="D"/>
+                  <input name="RN" num_pins="1"/>
+                  <output name="Q" num_pins="1" port_class="Q"/>
+                  <clock name="C" num_pins="1" port_class="clock"/>
+                  <T_setup value="66e-12" port="dffrn.D" clock="C"/>
+                  <T_setup value="66e-12" port="dffrn.RN" clock="C"/>
+                  <T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ff.D" output="dffrn.D"/>
+                  <direct name="direct2" input="ff.C" output="dffrn.C"/>
+                  <direct name="direct3" input="ff.R" output="dffrn.RN"/>
+                  <direct name="direct4" input="dffrn.Q" output="ff.Q"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.C"/>
+              <direct name="direct4" input="ble4.reset" output="ff.R"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+            <direct name="direct4" input="fle.reset" output="ble4.reset"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk clb.I" output="fle[3:0].clk">
+        </complete>
+        <complete name="resets" input="clb.reset" output="fle[3:0].reset">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 1fb39f803b72e07ceb961272e8442fca1e8148c6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 19:52:58 -0800
Subject: [PATCH 04/18] [doc] updated vpr arch naming rules

---
 openfpga_flow/vpr_arch/README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md
index 479a359cc..ec4e6fd10 100644
--- a/openfpga_flow/vpr_arch/README.md
+++ b/openfpga_flow/vpr_arch/README.md
@@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s
 - registerable\_io: If I/Os are registerable (can be either combinational or sequential)
 - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax
 - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture
+- localClkGen: The clock signal of CLB can be generated by internal programmable resources
 - <feature\_size>: The technology node which the delay numbers are extracted from.
 - TileOrgz<Type>: How tile is organized. 
   * Top-left (Tl): the pins of a tile are placed on the top side and left side only

From 93107c752ab69d6e15ed05e5a6e64d46c5cfc26a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 19:53:15 -0800
Subject: [PATCH 05/18] [test] updating test case

---
 .../tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index 1cf981d22..d78597e11 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v

From 9e462d96e0d116ac07697442a70e69f212f5734a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 20:46:04 -0800
Subject: [PATCH 06/18] [arch] now use a dedicated input for locally generated
 clock signals

---
 .../vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
index 6822f473a..a01191372 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
@@ -101,6 +101,8 @@
         </equivalent_sites>
         <input name="I" num_pins="12" equivalent="full"/>
         <input name="reset" num_pins="1" is_non_clock_global="true"/>
+        <!-- A dedicated clock for locally generated clock signals -->
+        <input name="lclk" num_pins="1" equivalent="none"/>
         <output name="O" num_pins="8" equivalent="none"/>
         <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
@@ -275,6 +277,7 @@
     <pb_type name="clb">
       <input name="I" num_pins="12" equivalent="full"/>
       <input name="reset" num_pins="1"/>
+      <input name="lclk" num_pins="1" equivalent="none"/>
       <output name="O" num_pins="8" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe fracturable logic element.  
@@ -611,7 +614,7 @@
           <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
           <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
         </complete>
-        <complete name="clks" input="clb.clk clb.I" output="fle[3:0].clk">
+        <complete name="clks" input="clb.clk clb.lclk" output="fle[3:0].clk">
         </complete>
         <complete name="resets" input="clb.reset" output="fle[3:0].reset">
         </complete>

From 26f71656de775559eb00e28b78a918936fc52162 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 21:12:18 -0800
Subject: [PATCH 07/18] [test] update pin constraints

---
 .../k4_series/k4n4_clk_gen/config/pin_constraints.xml         | 4 ++++
 .../k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml   | 4 ----
 .../k4n4_clk_gen/config/repack_design_constraints.xml         | 3 ++-
 .../tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf | 2 +-
 4 files changed, 7 insertions(+), 6 deletions(-)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
 delete mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
new file mode 100644
index 000000000..0b33739fe
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
@@ -0,0 +1,4 @@
+<pin_constraints>
+  <set_io pin="op_clk[0]" net="clk_i"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
deleted file mode 100644
index 20a21d2cf..000000000
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
+++ /dev/null
@@ -1,4 +0,0 @@
-<pin_constraints>
-  <!-- Intended to be dummy -->
-</pin_constraints>
-
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
index 06a125111..76ca10a78 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
@@ -1,4 +1,5 @@
 <repack_design_constraints>
-  <!-- Intended to be dummy -->
+  <pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
+  <!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
 </repack_design_constraints>
 
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index d78597e11..d889031ed 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -36,7 +36,7 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench0_top = clk_divider
-bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

From 9222d085cd2f21ed0e84ad86d76fbc5b258dcb94 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 22:04:56 -0800
Subject: [PATCH 08/18] [test] now use local clock as one of the pins in a
 clock bus, but connected to global routing

---
 openfpga_flow/openfpga_arch/README.md         |   1 +
 ...N4_fracff_localClkGen_40nm_cc_openfpga.xml | 255 ++++++++++++++++++
 .../k4_series/k4n4_clk_gen/config/task.conf   |   2 +-
 ...ac_N4_tileable_fracff_localClkGen_40nm.xml |  11 +-
 4 files changed, 261 insertions(+), 8 deletions(-)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md
index e4bd7f1f9..0960d3f2d 100644
--- a/openfpga_flow/openfpga_arch/README.md
+++ b/openfpga_flow/openfpga_arch/README.md
@@ -29,6 +29,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
 - registerable\_io: If I/Os are registerable (can be either combinational or sequential)
 - stdcell: If circuit designs are built with standard cells only
 - tree\_mux: If routing multiplexers are built with a tree-like structure
+- localClkGen: The clock signal of CLB can be generated by internal programmable resources
 - <feature_size>: The technology node which the delay numbers are extracted from.
 - powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
 - GlobalTile<Int>Clk<Pin>: How many clocks are defined through global ports from physical tiles.
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
new file mode 100644
index 000000000..df8f9b37c
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
@@ -0,0 +1,255 @@
+<?xml version="1.0"?>
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="input" prefix="selb" lib_name="SI" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="output" prefix="QN" size="1"/>
+      <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <tile_annotations>
+    <global_port name="op_clk" tile_port="clb.clk[1]" is_clock="true" default_val="0">
+      <tile name="clb" port="clk[1]"/>
+    </global_port>
+    <global_port name="op_reset" is_reset="true" default_val="0">
+      <tile name="clb" port="reset"/>
+    </global_port>
+  </tile_annotations>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
+      <port name="clk" physical_mode_port="C"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
+      <port name="RN" physical_mode_port="R"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
+      <port name="clk" physical_mode_port="C"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
+      <port name="RN" physical_mode_port="R"/>
+    </pb_type>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index d889031ed..12ad1855b 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
 
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
index a01191372..9d4d8d737 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
@@ -101,12 +101,10 @@
         </equivalent_sites>
         <input name="I" num_pins="12" equivalent="full"/>
         <input name="reset" num_pins="1" is_non_clock_global="true"/>
-        <!-- A dedicated clock for locally generated clock signals -->
-        <input name="lclk" num_pins="1" equivalent="none"/>
         <output name="O" num_pins="8" equivalent="none"/>
-        <clock name="clk" num_pins="1"/>
+        <clock name="clk" num_pins="2" equivalent="full"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="clk[1]" fc_type="frac" fc_val="0"/>
           <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
         </fc>
         <pinlocations pattern="spread"/>
@@ -277,9 +275,8 @@
     <pb_type name="clb">
       <input name="I" num_pins="12" equivalent="full"/>
       <input name="reset" num_pins="1"/>
-      <input name="lclk" num_pins="1" equivalent="none"/>
       <output name="O" num_pins="8" equivalent="none"/>
-      <clock name="clk" num_pins="1"/>
+      <clock name="clk" num_pins="2" equivalent="full"/>
       <!-- Describe fracturable logic element.  
              Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
              The outputs of the fracturable logic element can be optionally registered
@@ -614,7 +611,7 @@
           <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
           <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
         </complete>
-        <complete name="clks" input="clb.clk clb.lclk" output="fle[3:0].clk">
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
         </complete>
         <complete name="resets" input="clb.reset" output="fle[3:0].reset">
         </complete>

From 5aa85d82e6be15d0bf06659aee72c92a2ce8432d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 22:07:45 -0800
Subject: [PATCH 09/18] [test] deploy the new test to basic regression tests

---
 openfpga_flow/regression_test_scripts/basic_reg_test.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index c1ddf8a4a..cc1aa9771 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -142,6 +142,8 @@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@
 echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs";
 run-task basic_tests/k4_series/k4n4_rstOnLut $@
 run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@
+echo -e "Testing K4N4 support clock generation by internal resources";
+run-task basic_tests/k4_series/k4n4_clk_gen $@
 
 echo -e "Testing different tile organizations";
 echo -e "Testing tiles with pins only on top and left sides";

From 297092f1fe93a752ae773c88d39cd78aafecb802 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 14 Jan 2023 22:12:00 -0800
Subject: [PATCH 10/18] [arch] now use a local clock as an input of a CLB

---
 ...4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml |  4 ++--
 .../k4_frac_N4_tileable_fracff_localClkGen_40nm.xml  | 12 ++++++++----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
index df8f9b37c..7a7154031 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
@@ -200,8 +200,8 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="op_clk" tile_port="clb.clk[1]" is_clock="true" default_val="0">
-      <tile name="clb" port="clk[1]"/>
+    <global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
+      <tile name="clb" port="clk"/>
     </global_port>
     <global_port name="op_reset" is_reset="true" default_val="0">
       <tile name="clb" port="reset"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
index 9d4d8d737..1b127942d 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
@@ -102,9 +102,11 @@
         <input name="I" num_pins="12" equivalent="full"/>
         <input name="reset" num_pins="1" is_non_clock_global="true"/>
         <output name="O" num_pins="8" equivalent="none"/>
-        <clock name="clk" num_pins="2" equivalent="full"/>
+        <!-- Local clock -->
+        <input name="lclk" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override port_name="clk[1]" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
           <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
         </fc>
         <pinlocations pattern="spread"/>
@@ -276,7 +278,9 @@
       <input name="I" num_pins="12" equivalent="full"/>
       <input name="reset" num_pins="1"/>
       <output name="O" num_pins="8" equivalent="none"/>
-      <clock name="clk" num_pins="2" equivalent="full"/>
+      <!-- Local clock -->
+      <input name="lclk" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
       <!-- Describe fracturable logic element.  
              Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
              The outputs of the fracturable logic element can be optionally registered
@@ -611,7 +615,7 @@
           <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
           <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
         </complete>
-        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        <complete name="clks" input="clb.lclk clb.clk" output="fle[3:0].clk">
         </complete>
         <complete name="resets" input="clb.reset" output="fle[3:0].reset">
         </complete>

From 4242c39b01fe3e6af3dcea96ac88cf4c3892c3db Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 14 Jan 2023 23:05:04 -0800
Subject: [PATCH 11/18] [core] fixed a bug in handling design constraints in
 repack

---
 openfpga/src/repack/repack.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 6dcc64a70..db282fde8 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -613,6 +613,18 @@ static void add_lb_router_nets(
       }
     } else if (design_constraints.unconstrained_net(constrained_net_name)) {
       constrained_atom_net_id = atom_net_id;
+      /* Skip for the net which has been constrained on other pins */
+      if (atom_net_id && !design_constraints.unconstrained_net(atom_ctx.nlist.net_name(atom_net_id))) {
+        VTR_LOGV(verbose,
+                 "Skip net '%s' on pin '%s[%d]' during repacking since it has been constrained to another pin\n",
+                 atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name,
+                 source_pb_pin->pin_number);
+        continue;
+      }
+      VTR_LOGV(verbose,
+               "Follow the same mapping results for net '%s' on pin '%s[%d]' during repacking (constrained net name is %s)\n",
+               atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name,
+               source_pb_pin->pin_number, constrained_net_name.c_str());
     }
 
     /* Bypass unmapped pins. There are 4 conditions to consider

From 2a0e512ac95c8055b48e2ce6aa0a419ba0cc692a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 14 Jan 2023 23:05:42 -0800
Subject: [PATCH 12/18] [code] format

---
 openfpga/src/repack/repack.cpp | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index db282fde8..c6d88ed1b 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -614,17 +614,21 @@ static void add_lb_router_nets(
     } else if (design_constraints.unconstrained_net(constrained_net_name)) {
       constrained_atom_net_id = atom_net_id;
       /* Skip for the net which has been constrained on other pins */
-      if (atom_net_id && !design_constraints.unconstrained_net(atom_ctx.nlist.net_name(atom_net_id))) {
+      if (atom_net_id && !design_constraints.unconstrained_net(
+                           atom_ctx.nlist.net_name(atom_net_id))) {
         VTR_LOGV(verbose,
-                 "Skip net '%s' on pin '%s[%d]' during repacking since it has been constrained to another pin\n",
-                 atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name,
-                 source_pb_pin->pin_number);
+                 "Skip net '%s' on pin '%s[%d]' during repacking since it has "
+                 "been constrained to another pin\n",
+                 atom_ctx.nlist.net_name(atom_net_id).c_str(),
+                 source_pb_pin->port->name, source_pb_pin->pin_number);
         continue;
       }
       VTR_LOGV(verbose,
-               "Follow the same mapping results for net '%s' on pin '%s[%d]' during repacking (constrained net name is %s)\n",
-               atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name,
-               source_pb_pin->pin_number, constrained_net_name.c_str());
+               "Follow the same mapping results for net '%s' on pin '%s[%d]' "
+               "during repacking (constrained net name is %s)\n",
+               atom_ctx.nlist.net_name(atom_net_id).c_str(),
+               source_pb_pin->port->name, source_pb_pin->pin_number,
+               constrained_net_name.c_str());
     }
 
     /* Bypass unmapped pins. There are 4 conditions to consider

From 14bb76ec87e098341d3565cf78cb20fe844e10e3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 14 Jan 2023 23:06:54 -0800
Subject: [PATCH 13/18] [test] remove verification steps for new test but leave
 a todo

---
 .../basic_tests/k4_series/k4n4_clk_gen/config/task.conf      | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index 12ad1855b..40d11964c 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -39,5 +39,6 @@ bench0_top = clk_divider
 bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=
+# FIXME: Enable this once VPR can accept clock routing for specific clock signals
+#end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 758cc7a0891b02b9f940a43d97aa6530cab7c1a2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 15 Jan 2023 11:44:48 -0800
Subject: [PATCH 14/18] [test] debugging

---
 .../local_clk_gen_example_script.openfpga     | 73 +++++++++++++++++++
 .../k4_series/k4n4_clk_gen/config/task.conf   |  6 +-
 2 files changed, 76 insertions(+), 3 deletions(-)
 create mode 100644 openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga

diff --git a/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga
new file mode 100644
index 000000000..2fb7e0f9d
--- /dev/null
+++ b/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga
@@ -0,0 +1,73 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINT_FILE} #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index 40d11964c..b9ed6ba5b 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -16,7 +16,7 @@ timeout_each_job = 3*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
@@ -40,5 +40,5 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.x
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 # FIXME: Enable this once VPR can accept clock routing for specific clock signals
-#end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From cab7e0490110a52bfea87aa2ef67010c951758f3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 15 Jan 2023 12:13:12 -0800
Subject: [PATCH 15/18] [core] fixed a bug in repacker to avoid routing
 constrained nets

---
 libs/libpcf/src/base/repack_design_constraints.cpp | 11 +++++++++++
 libs/libpcf/src/base/repack_design_constraints.h   |  2 ++
 openfpga/src/repack/repack.cpp                     |  4 ++--
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp
index 8e6fb52ac..75ad0b5ec 100644
--- a/libs/libpcf/src/base/repack_design_constraints.cpp
+++ b/libs/libpcf/src/base/repack_design_constraints.cpp
@@ -69,6 +69,17 @@ std::string RepackDesignConstraints::find_constrained_pin_net(
   return constrained_net_name;
 }
 
+openfpga::BasicPort RepackDesignConstraints::net_pin(const std::string& net) const {
+  openfpga::BasicPort constrained_pin;
+  for (const RepackDesignConstraintId& design_constraint : design_constraints()) {
+    if (net == repack_design_constraint_nets_[design_constraint]) {
+      constrained_pin = pin(design_constraint);
+      break;
+    }
+  }
+  return constrained_pin;
+}
+
 bool RepackDesignConstraints::empty() const {
   return 0 == repack_design_constraint_ids_.size();
 }
diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h
index 35c5a8a1a..31db9562d 100644
--- a/libs/libpcf/src/base/repack_design_constraints.h
+++ b/libs/libpcf/src/base/repack_design_constraints.h
@@ -72,6 +72,8 @@ class RepackDesignConstraints {
   /* Find a constrained net */
   std::string find_constrained_pin_net(const std::string& pb_type,
                                        const openfpga::BasicPort& pin) const;
+  /* Find the port to which a net is constrained to */
+  openfpga::BasicPort net_pin(const std::string& net) const;
 
   /* Check if there are any design constraints */
   bool empty() const;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index c6d88ed1b..d7047d608 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -614,8 +614,8 @@ static void add_lb_router_nets(
     } else if (design_constraints.unconstrained_net(constrained_net_name)) {
       constrained_atom_net_id = atom_net_id;
       /* Skip for the net which has been constrained on other pins */
-      if (atom_net_id && !design_constraints.unconstrained_net(
-                           atom_ctx.nlist.net_name(atom_net_id))) {
+      if (atom_net_id && design_constraints.net_pin(
+                           atom_ctx.nlist.net_name(atom_net_id)).is_valid()) {
         VTR_LOGV(verbose,
                  "Skip net '%s' on pin '%s[%d]' during repacking since it has "
                  "been constrained to another pin\n",

From ac8c0e243c544f1197f00b659554fd0e1c6f6d80 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 15 Jan 2023 12:13:59 -0800
Subject: [PATCH 16/18] [core] code format

---
 libs/libpcf/src/base/repack_design_constraints.cpp | 6 ++++--
 openfpga/src/repack/repack.cpp                     | 5 +++--
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp
index 75ad0b5ec..220a2d41c 100644
--- a/libs/libpcf/src/base/repack_design_constraints.cpp
+++ b/libs/libpcf/src/base/repack_design_constraints.cpp
@@ -69,9 +69,11 @@ std::string RepackDesignConstraints::find_constrained_pin_net(
   return constrained_net_name;
 }
 
-openfpga::BasicPort RepackDesignConstraints::net_pin(const std::string& net) const {
+openfpga::BasicPort RepackDesignConstraints::net_pin(
+  const std::string& net) const {
   openfpga::BasicPort constrained_pin;
-  for (const RepackDesignConstraintId& design_constraint : design_constraints()) {
+  for (const RepackDesignConstraintId& design_constraint :
+       design_constraints()) {
     if (net == repack_design_constraint_nets_[design_constraint]) {
       constrained_pin = pin(design_constraint);
       break;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index d7047d608..42e0d0bbc 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -614,8 +614,9 @@ static void add_lb_router_nets(
     } else if (design_constraints.unconstrained_net(constrained_net_name)) {
       constrained_atom_net_id = atom_net_id;
       /* Skip for the net which has been constrained on other pins */
-      if (atom_net_id && design_constraints.net_pin(
-                           atom_ctx.nlist.net_name(atom_net_id)).is_valid()) {
+      if (atom_net_id &&
+          design_constraints.net_pin(atom_ctx.nlist.net_name(atom_net_id))
+            .is_valid()) {
         VTR_LOGV(verbose,
                  "Skip net '%s' on pin '%s[%d]' during repacking since it has "
                  "been constrained to another pin\n",

From 13aed6fff515c07e9482f0aafd1b92a9ade90e4c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 15 Jan 2023 12:17:59 -0800
Subject: [PATCH 17/18] [test] still commment verification out

---
 .../tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index b9ed6ba5b..6e4b75067 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -40,5 +40,5 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.x
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 # FIXME: Enable this once VPR can accept clock routing for specific clock signals
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=
+#end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 2c9593c1d4ef43aa194d2865c2bbd5dc037856a0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 15 Jan 2023 13:09:40 -0800
Subject: [PATCH 18/18] [test] now use a new benchmark: discrete dffn to
 validate the clk gen locally feature

---
 .../discrete_dffn/discrete_dffn.blif          | 10 ++++++++
 .../discrete_dffn/discrete_dffn.v             | 23 +++++++++++++++++++
 .../config/dffn_pin_constraints.xml           |  5 ++++
 .../config/dffn_repack_design_constraints.xml |  5 ++++
 .../k4_series/k4n4_clk_gen/config/task.conf   | 19 ++++++++++-----
 5 files changed, 56 insertions(+), 6 deletions(-)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml

diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
new file mode 100644
index 000000000..317233080
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
@@ -0,0 +1,10 @@
+.model discrete_dffn
+.inputs clk_ni d_i
+.outputs d_o
+
+.names clk_ni int_clk
+0 1
+
+.subckt dff D=d_i Q=d_o C=int_clk 
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
new file mode 100644
index 000000000..fce53a8cd
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
@@ -0,0 +1,23 @@
+/////////////////////////////////////////
+//  Functionality: A FF with inverted clk. This is useful to test if an FPGA supports clock generation internally or an FPGA supports negative-edged clock
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module discrete_dffn(
+  clk_ni,
+  d_i,
+  d_o);
+input wire clk_ni;
+input wire d_i;
+output reg d_o;
+
+wire int_clk;
+
+assign int_clk = ~clk_ni;
+
+always @(posedge int_clk) begin
+  d_o <= d_i;
+end
+
+endmodule
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml
new file mode 100644
index 000000000..e0aeb4cd2
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml
@@ -0,0 +1,5 @@
+<pin_constraints>
+  <!-- Intend to be dummy -->
+  <!-- set_io pin="op_clk[0]" net="clk_ni"/ -->
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml
new file mode 100644
index 000000000..a84216e64
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml
@@ -0,0 +1,5 @@
+<repack_design_constraints>
+  <!-- pin_constraint pb_type="clb" pin="clk[0]" net="clk_ni"/ -->
+  <!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index 6e4b75067..5bffd2c6a 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -13,7 +13,8 @@ power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 3*60
-fpga_flow=yosys_vpr
+#fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga
@@ -25,7 +26,8 @@ openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_con
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
 
 [SYNTHESIS_PARAM]
 # Yosys script parameters
@@ -35,10 +37,15 @@ bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
-bench0_top = clk_divider
-bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
+bench0_top = discrete_dffn
+bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/dffn_pin_constraints.xml
+bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/dffn_repack_design_constraints.xml
+
+#bench1_top = clk_divider
+#bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 # FIXME: Enable this once VPR can accept clock routing for specific clock signals
-#end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=