diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index 8e6fb52ac..220a2d41c 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -69,6 +69,19 @@ std::string RepackDesignConstraints::find_constrained_pin_net( return constrained_net_name; } +openfpga::BasicPort RepackDesignConstraints::net_pin( + const std::string& net) const { + openfpga::BasicPort constrained_pin; + for (const RepackDesignConstraintId& design_constraint : + design_constraints()) { + if (net == repack_design_constraint_nets_[design_constraint]) { + constrained_pin = pin(design_constraint); + break; + } + } + return constrained_pin; +} + bool RepackDesignConstraints::empty() const { return 0 == repack_design_constraint_ids_.size(); } diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 35c5a8a1a..31db9562d 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -72,6 +72,8 @@ class RepackDesignConstraints { /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; + /* Find the port to which a net is constrained to */ + openfpga::BasicPort net_pin(const std::string& net) const; /* Check if there are any design constraints */ bool empty() const; diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 6dcc64a70..42e0d0bbc 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -613,6 +613,23 @@ static void add_lb_router_nets( } } else if (design_constraints.unconstrained_net(constrained_net_name)) { constrained_atom_net_id = atom_net_id; + /* Skip for the net which has been constrained on other pins */ + if (atom_net_id && + design_constraints.net_pin(atom_ctx.nlist.net_name(atom_net_id)) + .is_valid()) { + VTR_LOGV(verbose, + "Skip net '%s' on pin '%s[%d]' during repacking since it has " + "been constrained to another pin\n", + atom_ctx.nlist.net_name(atom_net_id).c_str(), + source_pb_pin->port->name, source_pb_pin->pin_number); + continue; + } + VTR_LOGV(verbose, + "Follow the same mapping results for net '%s' on pin '%s[%d]' " + "during repacking (constrained net name is %s)\n", + atom_ctx.nlist.net_name(atom_net_id).c_str(), + source_pb_pin->port->name, source_pb_pin->pin_number, + constrained_net_name.c_str()); } /* Bypass unmapped pins. There are 4 conditions to consider diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v b/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v new file mode 100644 index 000000000..c559f49d7 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v @@ -0,0 +1,28 @@ +///////////////////////////////////////// +// Functionality: A two-stage clock divider (Frequency is divided by 4) +// This is to test the clock generated locally by a LUT/FF +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_divider(clk_i, clk_o); + +input wire clk_i; +output reg clk_o; + +reg int_clk; + +initial begin + clk_o <= 0; + int_clk <= 0; +end + +always @(posedge clk_i) begin + int_clk <= ~int_clk; +end + +always @(posedge int_clk) begin + clk_o <= ~clk_o; +end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif new file mode 100644 index 000000000..317233080 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif @@ -0,0 +1,10 @@ +.model discrete_dffn +.inputs clk_ni d_i +.outputs d_o + +.names clk_ni int_clk +0 1 + +.subckt dff D=d_i Q=d_o C=int_clk + +.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v new file mode 100644 index 000000000..fce53a8cd --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v @@ -0,0 +1,23 @@ +///////////////////////////////////////// +// Functionality: A FF with inverted clk. This is useful to test if an FPGA supports clock generation internally or an FPGA supports negative-edged clock +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module discrete_dffn( + clk_ni, + d_i, + d_o); +input wire clk_ni; +input wire d_i; +output reg d_o; + +wire int_clk; + +assign int_clk = ~clk_ni; + +always @(posedge int_clk) begin + d_o <= d_i; +end + +endmodule diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index e4bd7f1f9..0960d3f2d 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -29,6 +29,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - stdcell: If circuit designs are built with standard cells only - tree\_mux: If routing multiplexers are built with a tree-like structure +- localClkGen: The clock signal of CLB can be generated by internal programmable resources - : The technology node which the delay numbers are extracted from. - powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating. - GlobalTileClk: How many clocks are defined through global ports from physical tiles. diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml new file mode 100644 index 000000000..7a7154031 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml @@ -0,0 +1,255 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga new file mode 100644 index 000000000..2fb7e0f9d --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga @@ -0,0 +1,73 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINT_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c1ddf8a4a..cc1aa9771 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -142,6 +142,8 @@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; run-task basic_tests/k4_series/k4n4_rstOnLut $@ run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ +echo -e "Testing K4N4 support clock generation by internal resources"; +run-task basic_tests/k4_series/k4n4_clk_gen $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml new file mode 100644 index 000000000..e0aeb4cd2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml new file mode 100644 index 000000000..a84216e64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml new file mode 100644 index 000000000..0b33739fe --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml new file mode 100644 index 000000000..76ca10a78 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf new file mode 100644 index 000000000..5bffd2c6a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf @@ -0,0 +1,51 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +#fpga_flow=yosys_vpr +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = discrete_dffn +bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/dffn_pin_constraints.xml +bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/dffn_repack_design_constraints.xml + +#bench1_top = clk_divider +#bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +# FIXME: Enable this once VPR can accept clock routing for specific clock signals +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 479a359cc..ec4e6fd10 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture +- localClkGen: The clock signal of CLB can be generated by internal programmable resources - : The technology node which the delay numbers are extracted from. - TileOrgz: How tile is organized. * Top-left (Tl): the pins of a tile are placed on the top side and left side only diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml new file mode 100644 index 000000000..1b127942d --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml @@ -0,0 +1,635 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +