From 7d83fc914c63c14b59c20ceddd2752cd25368d98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 6 Oct 2023 18:31:54 -0700 Subject: [PATCH] [core] ad a new test case --- ...reconfig_testbench_example_script.openfpga | 2 +- .../fpga_bitstream_reg_test.sh | 3 + .../config/task.conf | 1 + .../config/task.conf | 1 + .../config/task.conf | 1 + .../fpga_bitstream/trim_path/config/task.conf | 56 +++++++++++++++++++ .../trim_path/config/tile_config.xml | 1 + 7 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/fpga_bitstream/trim_path/config/task.conf create mode 100644 openfpga_flow/tasks/fpga_bitstream/trim_path/config/tile_config.xml diff --git a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga index 978feaa56..cdb981da2 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga @@ -45,7 +45,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.bit --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml ${OPENFPGA_FABRIC_BITSTREAM_OPTIONS} # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index f5bb9a78f..c27475b04 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -45,3 +45,6 @@ run-task fpga_bitstream/report_bitstream_distribution/custom_depth $@ echo -e "Testing bitstream file with don't care bits"; run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten $@ run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register $@ + +echo -e "Testing bitstream file with selective contents"; +run-task fpga_bitstream/trim_path $@ diff --git a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile/config/task.conf b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile/config/task.conf index c8f54dda0..2da309cac 100644 --- a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile/config/task.conf @@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=60 openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options= openfpga_add_fpga_core_module= +openfpga_fabric_bitstream_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml diff --git a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape/config/task.conf b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape/config/task.conf index 8967adc33..8eb945a23 100644 --- a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape/config/task.conf @@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=60 openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options= openfpga_add_fpga_core_module= +openfpga_fabric_bitstream_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileableL_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml diff --git a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf index a04c046d9..06aaf0e87 100644 --- a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf @@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping openfpga_add_fpga_core_module= +openfpga_fabric_bitstream_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/trim_path/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/trim_path/config/task.conf new file mode 100644 index 000000000..a9032b322 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/trim_path/config/task.conf @@ -0,0 +1,56 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on +openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose +openfpga_vpr_device=3x2 +openfpga_vpr_route_chan_width=60 +openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options= +openfpga_add_fpga_core_module= +openfpga_fabric_bitstream_options=--trim_path + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v +bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mac_2 +bench1_top = mac_4 +bench2_top = mac_6 +bench3_top = mac_8 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_bitstream/trim_path/config/tile_config.xml b/openfpga_flow/tasks/fpga_bitstream/trim_path/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/trim_path/config/tile_config.xml @@ -0,0 +1 @@ +