[core] syntax
This commit is contained in:
parent
0167d8a90d
commit
7cea95b209
|
@ -6,7 +6,7 @@
|
||||||
# Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
|
# Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
|
||||||
# md5sum of input file: 1db9d740309076fa51f61413bae1e072
|
# md5sum of input file: 1db9d740309076fa51f61413bae1e072
|
||||||
|
|
||||||
@0xb1073886de13324f;
|
@0xdae3749fdf603d4b;
|
||||||
using Cxx = import "/capnp/c++.capnp";
|
using Cxx = import "/capnp/c++.capnp";
|
||||||
$Cxx.namespace("ucap");
|
$Cxx.namespace("ucap");
|
||||||
|
|
||||||
|
|
|
@ -686,8 +686,8 @@ static void annotate_direct_circuit_models(
|
||||||
VprDeviceAnnotation& vpr_device_annotation, const bool& verbose_output) {
|
VprDeviceAnnotation& vpr_device_annotation, const bool& verbose_output) {
|
||||||
size_t count = 0;
|
size_t count = 0;
|
||||||
|
|
||||||
for (int idirect = 0; idirect < vpr_device_ctx.arch->num_directs; ++idirect) {
|
for (size_t idirect = 0; idirect < vpr_device_ctx.arch->directs.size(); ++idirect) {
|
||||||
std::string direct_name = vpr_device_ctx.arch->Directs[idirect].name;
|
std::string direct_name = vpr_device_ctx.arch->directs[idirect].name;
|
||||||
/* The name-to-circuit mapping is stored in either cb_switch-to-circuit or
|
/* The name-to-circuit mapping is stored in either cb_switch-to-circuit or
|
||||||
* sb_switch-to-circuit, Try to find one and update the device annotation
|
* sb_switch-to-circuit, Try to find one and update the device annotation
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -794,28 +794,28 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
|
||||||
TileDirect tile_direct;
|
TileDirect tile_direct;
|
||||||
|
|
||||||
/* Walk through each direct definition in the VPR arch */
|
/* Walk through each direct definition in the VPR arch */
|
||||||
for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
|
for (size_t idirect = 0; idirect < device_ctx.arch->directs.size(); ++idirect) {
|
||||||
ArchDirectId arch_direct_id =
|
ArchDirectId arch_direct_id =
|
||||||
arch_direct.direct(std::string(device_ctx.arch->Directs[idirect].name));
|
arch_direct.direct(std::string(device_ctx.arch->directs[idirect].name));
|
||||||
if (ArchDirectId::INVALID() == arch_direct_id) {
|
if (ArchDirectId::INVALID() == arch_direct_id) {
|
||||||
VTR_LOG_ERROR(
|
VTR_LOG_ERROR(
|
||||||
"Unable to find an annotation in openfpga architecture XML for "
|
"Unable to find an annotation in openfpga architecture XML for "
|
||||||
"<direct> '%s'!\n",
|
"<direct> '%s'!\n",
|
||||||
device_ctx.arch->Directs[idirect].name);
|
device_ctx.arch->directs[idirect].name.c_str());
|
||||||
exit(1);
|
exit(1);
|
||||||
}
|
}
|
||||||
/* Build from original VPR arch definition */
|
/* Build from original VPR arch definition */
|
||||||
if (e_direct_type::INNER_COLUMN_OR_ROW ==
|
if (e_direct_type::INNER_COLUMN_OR_ROW ==
|
||||||
arch_direct.type(arch_direct_id)) {
|
arch_direct.type(arch_direct_id)) {
|
||||||
build_inner_column_row_tile_direct(tile_direct,
|
build_inner_column_row_tile_direct(tile_direct,
|
||||||
device_ctx.arch->Directs[idirect],
|
device_ctx.arch->directs[idirect],
|
||||||
device_ctx, arch_direct_id, verbose);
|
device_ctx, arch_direct_id, verbose);
|
||||||
/* Skip those direct connections which belong part of a connection block
|
/* Skip those direct connections which belong part of a connection block
|
||||||
*/
|
*/
|
||||||
}
|
}
|
||||||
/* Build from OpenFPGA arch definition */
|
/* Build from OpenFPGA arch definition */
|
||||||
build_inter_column_row_tile_direct(
|
build_inter_column_row_tile_direct(
|
||||||
tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct,
|
tile_direct, device_ctx.arch->directs[idirect], device_ctx, arch_direct,
|
||||||
arch_direct_id, verbose);
|
arch_direct_id, verbose);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue