diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index b98d07224..20ea51ecd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -262,7 +262,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, * 1. a compact output * 2. a full-size output */ - dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch); + dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, + lb_dir_path, &Arch, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 064cb2623..5d20c5f2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -281,7 +281,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side) { + int border_side, + boolean is_explicit_mapping) { int iz; int temp_reserved_conf_bits_msb; int temp_iopad_lsb, temp_iopad_msb; @@ -343,7 +344,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "//----- Submodule of type_descriptor: %s -----\n", phy_block_type->name); /* Print a NULL logic block...*/ dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix, - phy_block_type->pb_graph_head, iz); + phy_block_type->pb_graph_head, iz, + is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); /* Switch Flag on dumping verilog module */ verilog_module_dumped = TRUE; @@ -512,7 +514,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int itype, iside, num_sides; int* stamped_spice_model_cnt = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL; @@ -534,20 +537,23 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iside = 0; iside < num_sides; iside++) { dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], iside); + &type_descriptors[itype], iside, + is_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { /* For CLB */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); continue; } else { /* For heterogenenous blocks */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 87eb33f78..852415d67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -5,12 +5,14 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side); + int border_side, + boolean is_explicit_mapping); void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index ea01fc03e..51a85edc8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1037,7 +1037,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; @@ -1261,7 +1262,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info, - fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1318,7 +1320,8 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, char* formatted_pin_prefix, t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iport, ipin; /* Check the file handler*/ @@ -1339,7 +1342,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1351,7 +1354,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ OUTPUT2OUTPUT_INTERC, &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1363,7 +1366,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1382,7 +1385,8 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index) { + int select_mode_index, + boolean is_explicit_mapping) { int ipb, jpb; t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; @@ -1416,7 +1420,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, cur_pb_graph_node, SPICE_PB_PORT_OUTPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* We check input_pins of child_pb_graph_node and its the input_edges * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node @@ -1432,12 +1436,12 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_INPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* TODO: for clock pins, we should do the same work */ dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_CLOCK, - cur_mode); + cur_mode, is_explicit_mapping); } } @@ -1582,7 +1586,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { + int pb_type_index, + boolean is_explicit_mapping) { int mode_index, ipb, jpb, child_mode_index; t_pb_type* cur_pb_type = NULL; char* subckt_name = NULL; @@ -1645,8 +1650,10 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Recursive*/ /* Refer to pack/output_clustering.c [LINE 392] */ /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, pass_on_prefix, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + dump_verilog_phy_pb_graph_node_rec( + cur_sram_orgz_info, fp, pass_on_prefix, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + jpb, is_explicit_mapping); /* Free */ my_free(pass_on_prefix); /* Make the current module has been dumped */ @@ -1872,7 +1879,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } } /* Print interconnections, set is_idle as TRUE*/ - dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index); + dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, + cur_pb_graph_node, mode_index, + is_explicit_mapping); /* Check each pins of pb_graph_node */ /* Check and update stamped_sram_cnt */ /* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1 @@ -1951,7 +1960,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + boolean is_explicit_mapping) { t_pb_graph_node* top_pb_graph_node = NULL; t_block* mapped_block = NULL; t_pb* top_pb = NULL; @@ -1978,7 +1988,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, } /* Recursively find all idle mode and print netlist*/ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, top_pb_graph_node, z); + dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, + top_pb_graph_node, z, is_explicit_mapping); return; } @@ -2464,7 +2475,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, int ix, int iy, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int subckt_name_str_len = 0; char* subckt_name = NULL; int iz; @@ -2517,7 +2529,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Comments: Grid [x][y]*/ fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz); /* Print a NULL logic block...*/ - dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, + grid[ix][iy].type, is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); } @@ -2687,7 +2700,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, */ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int ix, iy; /* Check the grid*/ @@ -2709,7 +2723,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, assert(IO_TYPE != grid[ix][iy].type); /* Ensure a valid usage */ assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } } @@ -2720,7 +2735,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Right side : x = nx + 1, y = 1 .. ny*/ @@ -2728,7 +2744,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Bottom side : x = 1 .. nx + 1, y = 0 */ @@ -2736,14 +2753,16 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Left side: x = 0, y = 1 .. ny*/ ix = 0; for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Output a header file for all the logic blocks */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 42db03fb0..f5e45c2a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -58,13 +58,15 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode); + t_mode* cur_mode, + boolean is_explicit_mapping); void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index); + int select_mode_index, + boolean is_explicit_mapping); void dump_verilog_pb_graph_primitive_node(FILE* fp, char* subckt_prefix, @@ -84,7 +86,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); + int pb_type_index, + boolean is_explicit_mapping); void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -101,7 +104,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor); + t_type_ptr type_descriptor, + boolean is_explicit_mapping); void dump_verilog_grid_pins(FILE* fp, int x, int y, @@ -138,7 +142,8 @@ void dump_verilog_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int ix, int iy, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -147,7 +152,8 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, t_type_ptr type_descriptor); void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, - char* subckt_dir, t_arch* arch); + char* subckt_dir, t_arch* arch, + boolean is_explicit_mapping); void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, t_pb_graph_node* target_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 9616461b2..03a749747 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -694,7 +694,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index) { + int switch_index, + boolean is_explicit_mapping) { int inode, side, index, input_cnt = 0; int grid_x, grid_y; t_spice_model* verilog_model = NULL; @@ -837,7 +838,9 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1068,17 +1071,31 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".in("); + fprintf(fp, "%s_size%d_%d_inbus), ", + verilog_model->prefix, mux_size, verilog_model->cnt); + } + else { fprintf(fp, "%s_size%d_%d_inbus, ", verilog_model->prefix, mux_size, verilog_model->cnt); - + } /* Output port */ - dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".out("); + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + fprintf(fp, ")"); + } + else { + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + } /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -1327,7 +1344,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + boolean is_explicit_mapping) { int sb_x, sb_y; int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1370,7 +1388,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Print the multiplexer, fan_in >= 2 */ dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); } /*Nothing should be done else*/ /* Free */ @@ -2352,7 +2371,8 @@ static void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_sb* cur_sb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -2485,7 +2505,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info ||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type)); /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { - dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, cur_sb_info->chan_rr_node[side][itrack]); + dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, + cur_sb_info->chan_rr_node[side][itrack], + is_explicit_mapping); } } } @@ -2768,7 +2790,8 @@ static void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int mux_level, path_id, switch_index; @@ -2907,7 +2930,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -2995,7 +3020,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int inode, mux_level, path_id, switch_index; @@ -3137,7 +3163,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -3224,7 +3252,8 @@ static void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3237,7 +3266,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3247,7 +3277,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3264,7 +3295,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3389,7 +3421,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o static void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_cb, t_rr_type cb_type) { + const RRGSB& rr_cb, t_rr_type cb_type, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; @@ -3499,7 +3532,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, rr_gsb, cb_type, - rr_gsb.get_ipin_node(cb_ipin_side, inode)); + rr_gsb.get_ipin_node(cb_ipin_side, inode), + is_explicit_mapping); } } @@ -3552,7 +3586,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; @@ -3725,7 +3760,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert(NULL != cur_cb_info->ipin_rr_node[side]); for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, cur_cb_info, - cur_cb_info->ipin_rr_node[side][inode]); + cur_cb_info->ipin_rr_node[side][inode], + is_explicit_mapping); } } @@ -3867,8 +3903,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 0; iy < (ny + 1); iy++) { /* vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); */ update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, + subckt_dir, &(sb_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -3886,7 +3924,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANX, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } /* TODO: when we follow a tile organization, * updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */ @@ -3900,7 +3940,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Y - channels [1...ny][0..nx]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANY, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { @@ -3919,8 +3961,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cbx_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -3932,8 +3977,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cby_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 1cfd449b4..52ac54cc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -40,7 +40,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index); + int switch_index, + boolean is_explicit_mapping); int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info, int chan_side, @@ -54,7 +55,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + boolean is_explicit_mapping); int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info); @@ -68,7 +70,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_syn_verilog_opts fpga_verilog_opts, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_connection_box_short_interc(FILE* fp, @@ -78,12 +81,14 @@ void dump_verilog_connection_box_short_interc(FILE* fp, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, @@ -121,7 +126,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 58f30aa43..fefad5466 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2549,7 +2549,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2569,30 +2570,58 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m /* FOR Scan-chain, we need regular output of a scan-chain FF * We do not need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; case SPICE_SRAM_MEMORY_BANK: /* configuration wire bus */ /* First bus is for sram_out in CMOS MUX * We need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", @@ -2608,7 +2637,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2628,9 +2658,11 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_config_bus_ports(fp, mux_spice_model, cur_sram_orgz_info, mux_size, cur_num_sram, - num_mux_reserved_conf_bits, num_mux_conf_bits); + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: + /*TODO: Do explicit mapping for the RRAM*/ /* configuration wire bus */ fprintf(fp, "%s_size%d_%d_configbus0, ", mux_spice_model->prefix, mux_size, mux_spice_model->cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 282f4cfaa..5485ad97f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -187,13 +187,15 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb,