From 7c487eadc90a38381cef980326154b315e4403f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 16:58:23 -0700 Subject: [PATCH] [core] now clock network keep port info in a native data structure --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 12 +++++------- libs/libclkarchopenfpga/src/base/clock_network.h | 6 +++--- .../src/io/read_xml_clock_network.cpp | 9 ++++++--- .../src/io/write_xml_clock_network.cpp | 6 +++--- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 6f254530b..e95df9f68 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -372,7 +372,7 @@ std::vector ClockNetwork::tree_taps( return tree_taps_[tree_id]; } -std::string ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { +BasicPort ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { VTR_ASSERT(valid_tap_id(tap_id)); return tap_from_ports_[tap_id]; } @@ -470,17 +470,15 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( for (ClockTapId tap_id : tree_taps_[tree_id]) { VTR_ASSERT(valid_tap_id(tap_id)); /* Filter out unmatched from ports. Expect [clk_pin_id:clk_pin_id] */ - std::string tap_from_port_name = tap_from_ports_[tap_id]; - PortParser from_port_parser(tap_from_port_name); - BasicPort from_port = from_port_parser.port(); + BasicPort from_port = tap_from_ports_[tap_id]; if (!from_port.is_valid()) { VTR_LOG_ERROR("Invalid from port name '%s' whose index is not valid\n", - tap_from_port_name.c_str()); + from_port.to_verilog_string().c_str()); exit(1); } if (from_port.get_width() != 1) { VTR_LOG_ERROR("Invalid from port name '%s' whose width is not 1\n", - tap_from_port_name.c_str()); + from_port.to_verilog_string().c_str()); exit(1); } if (from_port.get_lsb() != size_t(clk_pin_id)) { @@ -792,7 +790,7 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( } ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, - const std::string& from_port, + const BasicPort& from_port, const std::string& to_port) { VTR_ASSERT(valid_tree_id(tree_id)); /* TODO: Consider find existing tap template and avoid duplication in storage diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 242720dce..ebfcbf038 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -144,7 +144,7 @@ class ClockNetwork { */ std::vector tree_taps(const ClockTreeId& tree_id) const; /* Return the source ports for a given tap */ - std::string tap_from_port(const ClockTapId& tap_id) const; + BasicPort tap_from_port(const ClockTapId& tap_id) const; /* Return the destination ports for a given tap */ std::string tap_to_port(const ClockTapId& tap_id) const; /* Find the type of tap point: @@ -224,7 +224,7 @@ class ClockNetwork { const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, const std::string& internal_driver_port); ClockTapId add_tree_tap(const ClockTreeId& tree_id, - const std::string& from_port, + const BasicPort& from_port, const std::string& to_port); bool set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb); @@ -319,7 +319,7 @@ class ClockNetwork { vtr::vector internal_driver_ports_; /* Basic information about tap */ vtr::vector tap_ids_; - vtr::vector tap_from_ports_; + vtr::vector tap_from_ports_; vtr::vector tap_to_ports_; vtr::vector> tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 4d47ad18e..c56b152fd 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -42,7 +42,8 @@ static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + PortParser from_port_parser(from_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); } /******************************************************************** @@ -62,8 +63,9 @@ static void read_xml_clock_tree_tap_type_single( std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); + PortParser from_port_parser(from_pin_name); ClockTapId tap_id = - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); /* Single tap only require a coordinate */ size_t tap_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -93,8 +95,9 @@ static void read_xml_clock_tree_tap_type_region( std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); + PortParser from_port_parser(from_pin_name); ClockTapId tap_id = - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); /* Region require a bounding box */ size_t tap_start_x = diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 3473a6350..fbdea521d 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -35,7 +35,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); fp << "/>" @@ -46,7 +46,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -61,7 +61,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX,