From faa222f2c178f693789631fe1758051db088a333 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 25 Sep 2024 18:42:04 +0800 Subject: [PATCH 01/23] create capnp folder --- libs/CMakeLists.txt | 1 + libs/libopenfpgacapnproto/CMakeLists.txt | 90 +++++++++++ libs/libopenfpgacapnproto/README.md | 84 +++++++++++ libs/libopenfpgacapnproto/gen/README.gen.md | 4 + .../gen/unique_blocks_uxsdcxx.capnp | 29 ++++ .../intra_cluster_serdes.h | 82 ++++++++++ libs/libopenfpgacapnproto/mmap_file.cpp | 39 +++++ libs/libopenfpgacapnproto/mmap_file.h | 19 +++ libs/libopenfpgacapnproto/ndmatrix_serdes.h | 141 ++++++++++++++++++ libs/libopenfpgacapnproto/serdes_utils.cpp | 22 +++ libs/libopenfpgacapnproto/serdes_utils.h | 20 +++ 11 files changed, 531 insertions(+) create mode 100644 libs/libopenfpgacapnproto/CMakeLists.txt create mode 100644 libs/libopenfpgacapnproto/README.md create mode 100644 libs/libopenfpgacapnproto/gen/README.gen.md create mode 100644 libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp create mode 100644 libs/libopenfpgacapnproto/intra_cluster_serdes.h create mode 100644 libs/libopenfpgacapnproto/mmap_file.cpp create mode 100644 libs/libopenfpgacapnproto/mmap_file.h create mode 100644 libs/libopenfpgacapnproto/ndmatrix_serdes.h create mode 100644 libs/libopenfpgacapnproto/serdes_utils.cpp create mode 100644 libs/libopenfpgacapnproto/serdes_utils.h diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index 537a46357..de555d3af 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -10,3 +10,4 @@ add_subdirectory(libpcf) add_subdirectory(libbusgroup) add_subdirectory(libnamemanager) add_subdirectory(libtileconfig) +add_subdirectory(libopenfpgacapnproto) diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt new file mode 100644 index 000000000..401267409 --- /dev/null +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -0,0 +1,90 @@ +include(GNUInstallDirs) + +if(NOT MSCV) + # These flags generate noisy but non-bug warnings when using lib kj, + # supress them. + set(WARN_FLAGS_TO_DISABLE + -Wno-undef + -Wno-non-virtual-dtor + ) + foreach(flag ${WARN_FLAGS_TO_DISABLE}) + CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag}) + if(CXX_COMPILER_SUPPORTS_${flag}) + #Flag supported, so enable it + add_compile_options(${flag}) + endif() + endforeach() +endif() + +# Create generated headers from capnp schema files +# +# Each schema used should appear here. +set(CAPNP_DEFS + gen/unique_blocks_uxsdcxx.capnp +) + +capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS + ${CAPNP_DEFS} +) + + +set(IC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../vtr-verilog-to-routing/libs/EXTERNAL/libinterchange/interchange) +set(CAPNPC_SRC_PREFIX ${IC_DIR}) + +find_program(WGET wget REQUIRED) +find_package(ZLIB REQUIRED) + +# Add Java schema +set(JAVA_SCHEMA ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema/capnp/java.capnp) +add_custom_command( + OUTPUT ${JAVA_SCHEMA} + COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema/capnp/ + COMMAND ${WGET} + https://raw.githubusercontent.com/capnproto/capnproto-java/master/compiler/src/main/schema/capnp/java.capnp + -O ${JAVA_SCHEMA} +) + + +set(CAPNPC_IMPORT_DIRS) +list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema) + +set(IC_PROTOS) +set(IC_SRCS) +set(IC_HDRS) +foreach(PROTO ${IC_PROTOS}) + capnp_generate_cpp( + IC_SRC + IC_HDR + ${IC_DIR}/${PROTO} + ) + list(APPEND IC_SRCS ${IC_SRC}) + list(APPEND IC_HDRS ${IC_HDR}) + list(APPEND CAPNP_DEFS ${IC_DIR}/${PROTO}) +endforeach() + + +install(FILES ${CAPNP_DEFS} DESTINATION ${CMAKE_INSTALL_DATADIR}/openfpga) + +add_library(libopenfpgacapnproto STATIC + ${CAPNP_SRCS} + ${IC_SRCS} + mmap_file.h + mmap_file.cpp + serdes_utils.h + serdes_utils.cpp + ) + + +add_dependencies(libopenfpgacapnproto + get_java_capnp_schema) + + +target_include_directories(libopenfpgacapnproto PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_BINARY_DIR}/gen + ) +target_link_libraries(libopenfpgacapnproto + libopenfpgautil + CapnProto::capnp +) diff --git a/libs/libopenfpgacapnproto/README.md b/libs/libopenfpgacapnproto/README.md new file mode 100644 index 000000000..38187e075 --- /dev/null +++ b/libs/libopenfpgacapnproto/README.md @@ -0,0 +1,84 @@ +Capnproto usage in VTR +====================== + +Capnproto is a data serialization framework designed for portabliity and speed. +In VPR, capnproto is used to provide binary formats for internal data +structures that can be computed once, and used many times. Specific examples: + - rrgraph + - Router lookahead data + - Place matrix delay estimates + +What is capnproto? +================== + +capnproto can be broken down into 3 parts: + - A schema language + - A code generator + - A library + +The schema language is used to define messages. Each message must have an +explcit capnproto schema, which are stored in files suffixed with ".capnp". +The capnproto documentation for how to write these schema files can be found +here: https://capnproto.org/language.html + +The schema by itself is not especially useful. In order to read and write +messages defined by the schema in a target language (e.g. C++), a code +generation step is required. Capnproto provides a cmake function for this +purpose, `capnp_generate_cpp`. This generates C++ source and header files. +These source and header files combined with the capnproto C++ library, enables +C++ code to read and write the messages matching a particular schema. The C++ +library API can be found here: https://capnproto.org/cxx.html + +Contents of libvtrcapnproto +=========================== + +libvtrcapnproto should contain two elements: + - Utilities for working capnproto messages in VTR + - Generate source and header files of all capnproto messages used in VTR + +I/O Utilities +------------- + +Capnproto does not provide IO support, instead it works from arrays (or file +descriptors). To avoid re-writing this code, libvtrcapnproto provides two +utilities that should be used whenever reading or writing capnproto message to +disk: + - `serdes_utils.h` provides the writeMessageToFile function - Writes a + capnproto message to disk. + - `mmap_file.h` provides MmapFile object - Maps a capnproto message from the + disk as a flat array. + +NdMatrix Utilities +------------------ + +A common datatype which appears in many data structures that VPR might want to +serialize is the generic type `vtr::NdMatrix`. `ndmatrix_serdes.h` provides +generic functions ToNdMatrix and FromNdMatrix, which can be used to generically +convert between the provideid capnproto message `Matrix` and `vtr::NdMatrix`. + +Capnproto schemas +----------------- + +libvtrcapnproto should contain all capnproto schema definitions used within +VTR. To add a new schema: +1. Add the schema to git in `libs/libvtrcapnproto/` +2. Add the schema file name to `capnp_generate_cpp` invocation in + `libs/libvtrcapnproto/CMakeLists.txt`. + +The schema will be available in the header file `schema filename>.h`. The +actual header file will appear in the CMake build directory +`libs/libvtrcapnproto` after `libvtrcapnproto` has been rebuilt. + +Writing capnproto binary files to text +====================================== + +The `capnp` tool (found in the CMake build directiory +`libs/EXTERNAL/capnproto/c++/src/capnp`) can be used to convert from a binary +capnp message to a textual form. + +Example converting VprOverrideDelayModel from binary to text: + +``` +capnp convert binary:text place_delay_model.capnp VprOverrideDelayModel \ + < place_delay.bin > place_delay.txt +``` diff --git a/libs/libopenfpgacapnproto/gen/README.gen.md b/libs/libopenfpgacapnproto/gen/README.gen.md new file mode 100644 index 000000000..838b546de --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/README.gen.md @@ -0,0 +1,4 @@ +`rr_graph_uxsdcxx.capnp` is generated via uxsdcxx and is checked in to +avoid requiring python3 and the uxsdcxx depedencies to build VPR. + +See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details. diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp new file mode 100644 index 000000000..ff3d8285d --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -0,0 +1,29 @@ +# This file is generated by uxsdcap 0.1.0. +# https://github.com/duck2/uxsdcxx +# Modify only if your build process doesn't involve regenerating this file. +# +# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 + +@0xa136dddfdd48783b; +using Cxx = import "/capnp/c++.capnp"; +$Cxx.namespace("uniqueblockcap"); + +enum BlockType { + cbx @0; + cby @1; + sb @2; +} + +struct BlockInfo { + type @0: BlockType; + x @1: Int32; + y @2: Int32; +} + + +struct InstanceInfo { + x @0 :Int32; + y @1 :Int32; +} diff --git a/libs/libopenfpgacapnproto/intra_cluster_serdes.h b/libs/libopenfpgacapnproto/intra_cluster_serdes.h new file mode 100644 index 000000000..f5579fc8c --- /dev/null +++ b/libs/libopenfpgacapnproto/intra_cluster_serdes.h @@ -0,0 +1,82 @@ +// +// Created by amin on 1/17/23. +// + +#ifndef VTR_INTRA_CLUSTER_SERDES_H +#define VTR_INTRA_CLUSTER_SERDES_H + +#include +#include +#include + +#include "vtr_ndmatrix.h" +#include "vpr_error.h" +#include "matrix.capnp.h" +#include "map_lookahead.capnp.h" +#include "vpr_types.h" +#include "router_lookahead_map_utils.h" + +template +void toVector(std::vector& vec_out, + const typename capnp::List::Reader& m_in, + const std::function&, + int, + const ElemType&)>& copy_fun) { + int size = m_in.size(); + vec_out.resize(size); + for(int idx = 0; idx < size; idx++) { + copy_fun(vec_out, idx, m_in[idx]); + } +} + +template +void toUnorderedMap( + std::unordered_map& map_in, + const int begin_flat_idx, + const int end_flat_idx, + const typename capnp::List::Reader& m_out_key, + const typename capnp::List::Reader& m_out_val, + const std::function&, + const KeyType&, + const typename CapValType::Reader&)>& copy_fun) { + + for(int flat_idx = begin_flat_idx; flat_idx < end_flat_idx; flat_idx++) { + copy_fun(map_in, m_out_key[flat_idx], m_out_val[flat_idx]); + } +} + +template +void fromVector(typename capnp::List::Builder& m_out, + const std::vector& vec_in, + const std::function::Builder&, + int, + const ElemType&)>& copy_fun) { + + for(int idx = 0; idx < (int)vec_in.size(); idx++) { + copy_fun(m_out, idx, vec_in[idx]); + } +} + +template +void FromUnorderedMap( + typename capnp::List::Builder& m_out_key, + typename capnp::List::Builder& m_out_val, + const KeyType out_offset, + const std::unordered_map& map_in, + const std::function::Builder&, + typename capnp::List::Builder&, + int, + const KeyType&, + const CostType&)>& copy_fun) { + + int flat_idx = out_offset; + for (const auto& entry : map_in) { + copy_fun(m_out_key, m_out_val, flat_idx, entry.first, entry.second); + flat_idx++; + } +} + + + + +#endif //VTR_INTRA_CLUSTER_SERDES_H diff --git a/libs/libopenfpgacapnproto/mmap_file.cpp b/libs/libopenfpgacapnproto/mmap_file.cpp new file mode 100644 index 000000000..e77c56366 --- /dev/null +++ b/libs/libopenfpgacapnproto/mmap_file.cpp @@ -0,0 +1,39 @@ +#include "mmap_file.h" +#include "vtr_error.h" +#include "vtr_util.h" + +#include +#include +#ifndef _WIN32 + #include +#endif +#include + +#include "kj/filesystem.h" + +MmapFile::MmapFile(const std::string& file) + : size_(0) { + try { + auto fs = kj::newDiskFilesystem(); + auto path = fs->getCurrentPath().evalNative(file); + + const auto& dir = fs->getRoot(); + auto stat = dir.lstat(path); + auto f = dir.openFile(path); + size_ = stat.size; + data_ = f->mmap(0, stat.size); + } catch (kj::Exception& e) { + throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); + } +} + +const kj::ArrayPtr MmapFile::getData() const { + if ((size_ % sizeof(::capnp::word)) != 0) { + throw vtr::VtrError( + vtr::string_fmt("size_ %d is not a multiple of capnp::word", size_), + __FILE__, __LINE__); + } + + return kj::arrayPtr(reinterpret_cast(data_.begin()), + size_ / sizeof(::capnp::word)); +} diff --git a/libs/libopenfpgacapnproto/mmap_file.h b/libs/libopenfpgacapnproto/mmap_file.h new file mode 100644 index 000000000..ee1a93e83 --- /dev/null +++ b/libs/libopenfpgacapnproto/mmap_file.h @@ -0,0 +1,19 @@ +#ifndef MMAP_FILE_H_ +#define MMAP_FILE_H_ + +#include +#include "capnp/message.h" +#include "kj/array.h" + +// Platform independent mmap, useful for reading large capnp's. +class MmapFile { + public: + explicit MmapFile(const std::string& file); + const kj::ArrayPtr getData() const; + + private: + size_t size_; + kj::Array data_; +}; + +#endif /* MMAP_FILE_H_ */ diff --git a/libs/libopenfpgacapnproto/ndmatrix_serdes.h b/libs/libopenfpgacapnproto/ndmatrix_serdes.h new file mode 100644 index 000000000..0282d4583 --- /dev/null +++ b/libs/libopenfpgacapnproto/ndmatrix_serdes.h @@ -0,0 +1,141 @@ +#ifndef NDMATRIX_SERDES_H_ +#define NDMATRIX_SERDES_H_ +// Provide generic functions for serializing vtr::NdMatrix to and from Cap'n +// proto Matrix. +// +// Functions: +// ToNdMatrix - Converts Matrix capnproto message to vtr::NdMatrix +// FromNdMatrix - Converts vtr::NdMatrix to Matrix capnproto +// +// Example: +// +// Schema: +// +// using Matrix = import "matrix.capnp"; +// +// +// struct Test { +// struct Vec2 { +// x @0 :Float32; +// y @1 :Float32; +// } +// vectors @0 :Matrix.Matrix(Vec2) +// } +// +// C++: +// +// struct Vec2 { +// float x; +// float y; +// }; +// +// static void ToVec2(Vec2 *out, const Test::Vec2::Reader& in) { +// out->x = in.getX(); +// out->y = in.getY(); +// } +// +// static void FromVec2(Test::Vec2::Builder* out, const Vec2 &in) { +// out->setX(in.x); +// out->setY(in.y); +// } +// +// void example(std::string file) { +// vtr::NdMatrix mat_in({3, 3, 3}, {2, 3}); +// +// ::capnp::MallocMessageBuilder builder; +// auto test = builder.initRoot(); +// auto vectors = test.getVectors(); +// +// FromNdMatrix<3, Test::Vec2, Vec2>(&vectors, mat_in, FromVec2); +// writeMessageToFile(file, &builder); +// +// MmapFile f(file); +// ::capnp::FlatArrayMessageReader reader(f.getData()); +// auto test = reader.getRoot(); +// +// vtr::NdMatrix mat_out; +// ToNdMatrix<3, Test::Vec2, Vec2>(&mat_out, test.getVectors(), FromVec2); +// } +#include +#include "vtr_ndmatrix.h" +#include "vpr_error.h" +#include "matrix.capnp.h" + +// Generic function to convert from Matrix capnproto message to vtr::NdMatrix. +// +// Template arguments: +// N = Number of matrix dimensions, must be fixed. +// CapType = Source capnproto message type that is a single element the +// Matrix capnproto message. +// CType = Target C++ type that is a single element of vtr::NdMatrix. +// +// Arguments: +// m_out = Target vtr::NdMatrix. +// m_in = Source capnproto message reader. +// copy_fun = Function to convert from CapType to CType. +template +void ToNdMatrix( + vtr::NdMatrix* m_out, + const typename Matrix::Reader& m_in, + const std::function& copy_fun) { + const auto& dims = m_in.getDims(); + if (N != dims.size()) { + VPR_THROW(VPR_ERROR_OTHER, + "Wrong dimension of template N = %zu, m_in.getDims() = %zu", + N, dims.size()); + } + + std::array dim_sizes; + size_t required_elements = 1; + for (size_t i = 0; i < N; ++i) { + dim_sizes[i] = dims[i]; + required_elements *= dims[i]; + } + m_out->resize(dim_sizes); + + const auto& data = m_in.getData(); + if (data.size() != required_elements) { + VPR_THROW(VPR_ERROR_OTHER, + "Wrong number of elements, expected %zu, actual %zu", + required_elements, data.size()); + } + + for (size_t i = 0; i < required_elements; ++i) { + copy_fun(&m_out->get(i), data[i].getValue()); + } +} + +// Generic function to convert from vtr::NdMatrix to Matrix capnproto message. +// +// Template arguments: +// N = Number of matrix dimensions, must be fixed. +// CapType = Target capnproto message type that is a single element the +// Matrix capnproto message. +// CType = Source C++ type that is a single element of vtr::NdMatrix. +// +// Arguments: +// m_out = Target capnproto message builder. +// m_in = Source vtr::NdMatrix. +// copy_fun = Function to convert from CType to CapType. +// +template +void FromNdMatrix( + typename Matrix::Builder* m_out, + const vtr::NdMatrix& m_in, + const std::function& copy_fun) { + size_t elements = 1; + auto dims = m_out->initDims(N); + for (size_t i = 0; i < N; ++i) { + dims.set(i, m_in.dim_size(i)); + elements *= dims[i]; + } + + auto data = m_out->initData(elements); + + for (size_t i = 0; i < elements; ++i) { + auto elem = data[i].getValue(); + copy_fun(&elem, m_in.get(i)); + } +} + +#endif /* NDMATRIX_SERDES_H_ */ diff --git a/libs/libopenfpgacapnproto/serdes_utils.cpp b/libs/libopenfpgacapnproto/serdes_utils.cpp new file mode 100644 index 000000000..2201fa584 --- /dev/null +++ b/libs/libopenfpgacapnproto/serdes_utils.cpp @@ -0,0 +1,22 @@ +#include "serdes_utils.h" + +#include +#include + +#include "vtr_error.h" +#include "kj/filesystem.h" + +void writeMessageToFile(const std::string& file, ::capnp::MessageBuilder* builder) { + try { + auto fs = kj::newDiskFilesystem(); + auto path = fs->getCurrentPath().evalNative(file); + + const auto& dir = fs->getRoot(); + auto f = dir.openFile(path, kj::WriteMode::CREATE | kj::WriteMode::MODIFY); + f->truncate(0); + auto f_app = kj::newFileAppender(std::move(f)); + capnp::writeMessage(*f_app, *builder); + } catch (kj::Exception& e) { + throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); + } +} diff --git a/libs/libopenfpgacapnproto/serdes_utils.h b/libs/libopenfpgacapnproto/serdes_utils.h new file mode 100644 index 000000000..723a14772 --- /dev/null +++ b/libs/libopenfpgacapnproto/serdes_utils.h @@ -0,0 +1,20 @@ +#ifndef SERDES_UTILS_H_ +#define SERDES_UTILS_H_ + +#include +#include +#include "capnp/serialize.h" + +// Platform indepedent way to file message to a file on disk. +void writeMessageToFile(const std::string& file, + ::capnp::MessageBuilder* builder); + +inline ::capnp::ReaderOptions default_large_capnp_opts() { + ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); + + /* Remove traversal limit */ + opts.traversalLimitInWords = std::numeric_limits::max(); + return opts; +} + +#endif /* SERDES_UTILS_H_ */ From 5174b7a3361f087f7563b400aa50ff4e0e9822dd Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 26 Sep 2024 17:39:52 +0800 Subject: [PATCH 02/23] add capnp for unique blocks and add write bin function --- libs/libopenfpgacapnproto/gen/README.gen.md | 4 +- .../gen/unique_blocks_uxsdcxx.capnp | 27 ++-- .../intra_cluster_serdes.h | 82 ---------- libs/libopenfpgacapnproto/ndmatrix_serdes.h | 141 ------------------ openfpga/CMakeLists.txt | 4 +- .../src/annotation/read_xml_unique_blocks.cpp | 6 + .../src/annotation/read_xml_unique_blocks.h | 5 +- .../annotation/write_xml_unique_blocks.cpp | 68 ++++++++- .../src/annotation/write_xml_unique_blocks.h | 2 + .../src/base/openfpga_build_fabric_template.h | 8 + 10 files changed, 109 insertions(+), 238 deletions(-) delete mode 100644 libs/libopenfpgacapnproto/intra_cluster_serdes.h delete mode 100644 libs/libopenfpgacapnproto/ndmatrix_serdes.h diff --git a/libs/libopenfpgacapnproto/gen/README.gen.md b/libs/libopenfpgacapnproto/gen/README.gen.md index 838b546de..8c08d1a30 100644 --- a/libs/libopenfpgacapnproto/gen/README.gen.md +++ b/libs/libopenfpgacapnproto/gen/README.gen.md @@ -1,4 +1,4 @@ -`rr_graph_uxsdcxx.capnp` is generated via uxsdcxx and is checked in to +`unique_blocks_uxsdcxx.capnp` is generated via uxsdcxx and is checked in to avoid requiring python3 and the uxsdcxx depedencies to build VPR. -See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details. + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp index ff3d8285d..0427aea15 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -11,19 +11,28 @@ using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("uniqueblockcap"); enum BlockType { - cbx @0; - cby @1; - sb @2; + cbx @0; + cby @1; + sb @2; } struct BlockInfo { - type @0: BlockType; - x @1: Int32; - y @2: Int32; + type @0: BlockType; + x @1: Int32; + y @2: Int32; } - struct InstanceInfo { - x @0 :Int32; - y @1 :Int32; + x @0: Int32; + y @1: Int32; +} + + +struct UniqueBlockPacked { + blockInfo @0: BlockInfo; + instanceList @1: List(InstanceInfo); +} + +struct UniqueBlockCompactInfo { + atomInfo @0: List(UniqueBlockPacked); } diff --git a/libs/libopenfpgacapnproto/intra_cluster_serdes.h b/libs/libopenfpgacapnproto/intra_cluster_serdes.h deleted file mode 100644 index f5579fc8c..000000000 --- a/libs/libopenfpgacapnproto/intra_cluster_serdes.h +++ /dev/null @@ -1,82 +0,0 @@ -// -// Created by amin on 1/17/23. -// - -#ifndef VTR_INTRA_CLUSTER_SERDES_H -#define VTR_INTRA_CLUSTER_SERDES_H - -#include -#include -#include - -#include "vtr_ndmatrix.h" -#include "vpr_error.h" -#include "matrix.capnp.h" -#include "map_lookahead.capnp.h" -#include "vpr_types.h" -#include "router_lookahead_map_utils.h" - -template -void toVector(std::vector& vec_out, - const typename capnp::List::Reader& m_in, - const std::function&, - int, - const ElemType&)>& copy_fun) { - int size = m_in.size(); - vec_out.resize(size); - for(int idx = 0; idx < size; idx++) { - copy_fun(vec_out, idx, m_in[idx]); - } -} - -template -void toUnorderedMap( - std::unordered_map& map_in, - const int begin_flat_idx, - const int end_flat_idx, - const typename capnp::List::Reader& m_out_key, - const typename capnp::List::Reader& m_out_val, - const std::function&, - const KeyType&, - const typename CapValType::Reader&)>& copy_fun) { - - for(int flat_idx = begin_flat_idx; flat_idx < end_flat_idx; flat_idx++) { - copy_fun(map_in, m_out_key[flat_idx], m_out_val[flat_idx]); - } -} - -template -void fromVector(typename capnp::List::Builder& m_out, - const std::vector& vec_in, - const std::function::Builder&, - int, - const ElemType&)>& copy_fun) { - - for(int idx = 0; idx < (int)vec_in.size(); idx++) { - copy_fun(m_out, idx, vec_in[idx]); - } -} - -template -void FromUnorderedMap( - typename capnp::List::Builder& m_out_key, - typename capnp::List::Builder& m_out_val, - const KeyType out_offset, - const std::unordered_map& map_in, - const std::function::Builder&, - typename capnp::List::Builder&, - int, - const KeyType&, - const CostType&)>& copy_fun) { - - int flat_idx = out_offset; - for (const auto& entry : map_in) { - copy_fun(m_out_key, m_out_val, flat_idx, entry.first, entry.second); - flat_idx++; - } -} - - - - -#endif //VTR_INTRA_CLUSTER_SERDES_H diff --git a/libs/libopenfpgacapnproto/ndmatrix_serdes.h b/libs/libopenfpgacapnproto/ndmatrix_serdes.h deleted file mode 100644 index 0282d4583..000000000 --- a/libs/libopenfpgacapnproto/ndmatrix_serdes.h +++ /dev/null @@ -1,141 +0,0 @@ -#ifndef NDMATRIX_SERDES_H_ -#define NDMATRIX_SERDES_H_ -// Provide generic functions for serializing vtr::NdMatrix to and from Cap'n -// proto Matrix. -// -// Functions: -// ToNdMatrix - Converts Matrix capnproto message to vtr::NdMatrix -// FromNdMatrix - Converts vtr::NdMatrix to Matrix capnproto -// -// Example: -// -// Schema: -// -// using Matrix = import "matrix.capnp"; -// -// -// struct Test { -// struct Vec2 { -// x @0 :Float32; -// y @1 :Float32; -// } -// vectors @0 :Matrix.Matrix(Vec2) -// } -// -// C++: -// -// struct Vec2 { -// float x; -// float y; -// }; -// -// static void ToVec2(Vec2 *out, const Test::Vec2::Reader& in) { -// out->x = in.getX(); -// out->y = in.getY(); -// } -// -// static void FromVec2(Test::Vec2::Builder* out, const Vec2 &in) { -// out->setX(in.x); -// out->setY(in.y); -// } -// -// void example(std::string file) { -// vtr::NdMatrix mat_in({3, 3, 3}, {2, 3}); -// -// ::capnp::MallocMessageBuilder builder; -// auto test = builder.initRoot(); -// auto vectors = test.getVectors(); -// -// FromNdMatrix<3, Test::Vec2, Vec2>(&vectors, mat_in, FromVec2); -// writeMessageToFile(file, &builder); -// -// MmapFile f(file); -// ::capnp::FlatArrayMessageReader reader(f.getData()); -// auto test = reader.getRoot(); -// -// vtr::NdMatrix mat_out; -// ToNdMatrix<3, Test::Vec2, Vec2>(&mat_out, test.getVectors(), FromVec2); -// } -#include -#include "vtr_ndmatrix.h" -#include "vpr_error.h" -#include "matrix.capnp.h" - -// Generic function to convert from Matrix capnproto message to vtr::NdMatrix. -// -// Template arguments: -// N = Number of matrix dimensions, must be fixed. -// CapType = Source capnproto message type that is a single element the -// Matrix capnproto message. -// CType = Target C++ type that is a single element of vtr::NdMatrix. -// -// Arguments: -// m_out = Target vtr::NdMatrix. -// m_in = Source capnproto message reader. -// copy_fun = Function to convert from CapType to CType. -template -void ToNdMatrix( - vtr::NdMatrix* m_out, - const typename Matrix::Reader& m_in, - const std::function& copy_fun) { - const auto& dims = m_in.getDims(); - if (N != dims.size()) { - VPR_THROW(VPR_ERROR_OTHER, - "Wrong dimension of template N = %zu, m_in.getDims() = %zu", - N, dims.size()); - } - - std::array dim_sizes; - size_t required_elements = 1; - for (size_t i = 0; i < N; ++i) { - dim_sizes[i] = dims[i]; - required_elements *= dims[i]; - } - m_out->resize(dim_sizes); - - const auto& data = m_in.getData(); - if (data.size() != required_elements) { - VPR_THROW(VPR_ERROR_OTHER, - "Wrong number of elements, expected %zu, actual %zu", - required_elements, data.size()); - } - - for (size_t i = 0; i < required_elements; ++i) { - copy_fun(&m_out->get(i), data[i].getValue()); - } -} - -// Generic function to convert from vtr::NdMatrix to Matrix capnproto message. -// -// Template arguments: -// N = Number of matrix dimensions, must be fixed. -// CapType = Target capnproto message type that is a single element the -// Matrix capnproto message. -// CType = Source C++ type that is a single element of vtr::NdMatrix. -// -// Arguments: -// m_out = Target capnproto message builder. -// m_in = Source vtr::NdMatrix. -// copy_fun = Function to convert from CType to CapType. -// -template -void FromNdMatrix( - typename Matrix::Builder* m_out, - const vtr::NdMatrix& m_in, - const std::function& copy_fun) { - size_t elements = 1; - auto dims = m_out->initDims(N); - for (size_t i = 0; i < N; ++i) { - dims.set(i, m_in.dim_size(i)); - elements *= dims[i]; - } - - auto data = m_out->initData(elements); - - for (size_t i = 0; i < elements; ++i) { - auto elem = data[i].getValue(); - copy_fun(&elem, m_in.get(i)); - } -} - -#endif /* NDMATRIX_SERDES_H_ */ diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 96c450876..f77e79139 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -44,7 +44,9 @@ target_link_libraries(libopenfpga libnamemanager libtileconfig libpugixml - libvpr) + libvpr + libopenfpgacapnproto + ) #Create the test executable add_executable(openfpga ${EXEC_SOURCE}) diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 6b3810602..e451328ff 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -154,4 +154,10 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, archfpga_throw(file_name, e.line(), "%s", e.what()); } } + +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + return 0; +} + } // namespace openfpga diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index 3e5e22c62..d5a0dcca8 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -15,7 +15,7 @@ /* Headers from libarchfpga */ #include "arch_error.h" #include "device_rr_gsb_utils.h" - +#include "unique_blocks_uxsdcxx.capnp.h" /******************************************************************** * This file includes the top-level functions of this library * which includes: @@ -35,5 +35,8 @@ void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); + +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output); } // namespace openfpga #endif diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index c7f0351d4..c1873a44f 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -1,10 +1,11 @@ +#include + #include - /* Headers from pugi XML library */ #include "pugixml.hpp" #include "pugixml_util.hpp" - +#include "serdes_utils.h" /* Headers from vtr util library */ #include "vtr_assert.h" #include "vtr_log.h" @@ -17,6 +18,7 @@ #include "openfpga_digest.h" #include "read_xml_util.h" #include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" #include "write_xml_unique_blocks.h" #include "write_xml_utils.h" @@ -187,4 +189,66 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, return CMD_EXEC_SUCCESS; } + +// int write_bin_atom_block(std::fstream& fp, +// const std::vector>& instance_map, +// const vtr::Point& unique_block_coord, +// std::string type, +// ucap::RrGraph::Builder &root) { + +// root.init +// write_xml_attribute(fp, "type", type.c_str()); +// write_xml_attribute(fp, "x", unique_block_coord.x()); +// write_xml_attribute(fp, "y", unique_block_coord.y()); + +// for (const auto& instance_info : instance_map) { +// if (instance_info.x() == unique_block_coord.x() && +// instance_info.y() == unique_block_coord.y()) { +// ; +// } else { +// openfpga::write_tab_to_file(fp, 2); +// fp << "(); + void* context; + int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX) + + device_rr_gsb.get_num_cb_unique_module(CHANY); + unique_blocks.initAtomInfo(num_unique_blocks); + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + + auto unique_block = unique_blocks[id]; + auto block_info = unique_block.initBlockInfo(); + block_info.setX(unique_block_coord.x()); + block_info.setY(unique_block_coord.y()); + block_info.setType(SB); + auto instance_list = unique_block.initInstanceList(instance_map.size()); + for (size_t instance_id = 0 ; instance_id < instance_map; instance_id ++){ + if (instance_map[instance_id].x() == unique_block_coord.x() && + instance_map[instance_id].y() == unique_block_coord.y()) { + ; + } else { + auto instance = instance_list[instance_id]; + instance.setX(instance_map[instance_id].x()); + instance.setY(instance_map[instance_id].y()); + } + } + } + writeMessageToFile(fname, &builder); + return 0; +} + } // namespace openfpga diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index 2fde43845..ca3433648 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -33,5 +33,7 @@ void report_unique_module_status_write( bool verbose_output); /*report status of written info*/ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); +int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output); } // namespace openfpga #endif diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 671b2043d..06d157ed5 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -500,6 +500,10 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, return read_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), file_name.c_str(), cmd_context.option_enable(cmd, opt_verbose)); + } else if (file_type == "bin") { + return read_bin_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); return CMD_EXEC_FATAL_ERROR; @@ -528,6 +532,10 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, return write_xml_unique_blocks(openfpga_ctx.device_rr_gsb(), file_name.c_str(), cmd_context.option_enable(cmd, opt_verbose)); + } else if (file_type == "bin") { + return write_bin_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); return CMD_EXEC_FATAL_ERROR; From 0cca4952bc23b42db98a973015e8103d95b22f37 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 26 Sep 2024 18:01:13 +0800 Subject: [PATCH 03/23] write bin format function (with bug) --- .../annotation/write_xml_unique_blocks.cpp | 98 ++++++++++++++----- 1 file changed, 76 insertions(+), 22 deletions(-) diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index c1873a44f..cd7548d41 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -225,29 +225,83 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); unique_blocks.initAtomInfo(num_unique_blocks); - for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { - const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); - const std::vector> instance_map = - device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + // for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + // const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + // const std::vector> instance_map = + // device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); - auto unique_block = unique_blocks[id]; - auto block_info = unique_block.initBlockInfo(); - block_info.setX(unique_block_coord.x()); - block_info.setY(unique_block_coord.y()); - block_info.setType(SB); - auto instance_list = unique_block.initInstanceList(instance_map.size()); - for (size_t instance_id = 0 ; instance_id < instance_map; instance_id ++){ - if (instance_map[instance_id].x() == unique_block_coord.x() && - instance_map[instance_id].y() == unique_block_coord.y()) { - ; - } else { - auto instance = instance_list[instance_id]; - instance.setX(instance_map[instance_id].x()); - instance.setY(instance_map[instance_id].y()); - } - } - } - writeMessageToFile(fname, &builder); + // auto unique_block = unique_blocks[id]; + // auto block_info = unique_block.initBlockInfo(); + // block_info.setX(unique_block_coord.x()); + // block_info.setY(unique_block_coord.y()); + // block_info.setType(SB); + // auto instance_list = unique_block.initInstanceList(instance_map.size()); + // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { + // if (instance_map[instance_id].x() == unique_block_coord.x() && + // instance_map[instance_id].y() == unique_block_coord.y()) { + // ; + // } else { + // auto instance = instance_list[instance_id]; + // instance.setX(instance_map[instance_id].x()); + // instance.setY(instance_map[instance_id].y()); + // } + // } + // } + + + // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); + // id < device_rr_gsb.get_num_sb_unique_module() + + // device_rr_gsb.get_num_cb_unique_module(CHANX); + // ++id) { + // const auto unique_block_coord = device_rr_gsb.get_cbx_unique_block_coord(id); + // const std::vector> instance_map = + // device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + + // auto unique_block = unique_blocks[id]; + // auto block_info = unique_block.initBlockInfo(); + // block_info.setX(unique_block_coord.x()); + // block_info.setY(unique_block_coord.y()); + // block_info.setType(SB); + // auto instance_list = unique_block.initInstanceList(instance_map.size()); + // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { + // if (instance_map[instance_id].x() == unique_block_coord.x() && + // instance_map[instance_id].y() == unique_block_coord.y()) { + // ; + // } else { + // auto instance = instance_list[instance_id]; + // instance.setX(instance_map[instance_id].x()); + // instance.setY(instance_map[instance_id].y()); + // } + // } + // } + + + // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); + // id < device_rr_gsb.get_num_sb_unique_module() + + // device_rr_gsb.get_num_cb_unique_module(CHANY); + // ++id) { + // const auto unique_block_coord = device_rr_gsb.get_cby_unique_block_coord(id); + // const std::vector> instance_map = + // device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + + // auto unique_block = unique_blocks[id]; + // auto block_info = unique_block.initBlockInfo(); + // block_info.setX(unique_block_coord.x()); + // block_info.setY(unique_block_coord.y()); + // block_info.setType(SB); + // auto instance_list = unique_block.initInstanceList(instance_map.size()); + // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { + // if (instance_map[instance_id].x() == unique_block_coord.x() && + // instance_map[instance_id].y() == unique_block_coord.y()) { + // ; + // } else { + // auto instance = instance_list[instance_id]; + // instance.setX(instance_map[instance_id].x()); + // instance.setY(instance_map[instance_id].y()); + // } + // } + // } + // writeMessageToFile(fname, &builder); return 0; } From 3fcdc10d3add724fa5200ed66d5b4eaac61fa70b Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 27 Sep 2024 11:34:57 +0800 Subject: [PATCH 04/23] write bin function no compile error --- .../gen/unique_blocks_uxsdcxx.capnp | 8 +- .../annotation/write_xml_unique_blocks.cpp | 103 ++++++++++-------- .../src/annotation/write_xml_unique_blocks.h | 5 + 3 files changed, 64 insertions(+), 52 deletions(-) diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp index 0427aea15..1a44cfc9d 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -18,13 +18,13 @@ enum BlockType { struct BlockInfo { type @0: BlockType; - x @1: Int32; - y @2: Int32; + x @1: UInt32; + y @2: UInt32; } struct InstanceInfo { - x @0: Int32; - y @1: Int32; + x @0: UInt32; + y @1: UInt32; } diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index cd7548d41..a92fc31b0 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -190,28 +190,26 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, return CMD_EXEC_SUCCESS; } -// int write_bin_atom_block(std::fstream& fp, -// const std::vector>& instance_map, +// int write_bin_atom_block(const std::vector>& instance_map, // const vtr::Point& unique_block_coord, -// std::string type, -// ucap::RrGraph::Builder &root) { - -// root.init -// write_xml_attribute(fp, "type", type.c_str()); -// write_xml_attribute(fp, "x", unique_block_coord.x()); -// write_xml_attribute(fp, "y", unique_block_coord.y()); - -// for (const auto& instance_info : instance_map) { -// if (instance_info.x() == unique_block_coord.x() && -// instance_info.y() == unique_block_coord.y()) { -// ; -// } else { -// openfpga::write_tab_to_file(fp, 2); -// fp << "> instance_map = - // device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + auto block_list = unique_blocks.initAtomInfo(num_unique_blocks); - // auto unique_block = unique_blocks[id]; - // auto block_info = unique_block.initBlockInfo(); - // block_info.setX(unique_block_coord.x()); - // block_info.setY(unique_block_coord.y()); - // block_info.setType(SB); - // auto instance_list = unique_block.initInstanceList(instance_map.size()); - // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { - // if (instance_map[instance_id].x() == unique_block_coord.x() && - // instance_map[instance_id].y() == unique_block_coord.y()) { - // ; - // } else { - // auto instance = instance_list[instance_id]; - // instance.setX(instance_map[instance_id].x()); - // instance.setY(instance_map[instance_id].y()); - // } - // } - // } + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + auto unique_block = block_list[id]; + + auto block_info = unique_block.initBlockInfo(); + block_info.setX(unique_block_coord.x()); + block_info.setY(unique_block_coord.y()); + block_info.setType(uniqueblockcap::BlockType::SB); + auto instance_list = unique_block.initInstanceList(instance_map.size()); + for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { + if (instance_map[instance_id].x() == unique_block_coord.x() && + instance_map[instance_id].y() == unique_block_coord.y()) { + ; + } else { + auto instance = instance_list[instance_id]; + instance.setX(instance_map[instance_id].x()); + instance.setY(instance_map[instance_id].y()); + } + } + + // int status_code = write_bin_atom_block(instance_map, unique_block_coord, + // uniqueblockcap::BlockType::SB, unique_block); + // if (status_code != 0) { + // VTR_LOG_ERROR("write cbx unique blocks into xml file failed!"); + // return CMD_EXEC_FATAL_ERROR; + // } + } // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); // id < device_rr_gsb.get_num_sb_unique_module() + // device_rr_gsb.get_num_cb_unique_module(CHANX); // ++id) { - // const auto unique_block_coord = device_rr_gsb.get_cbx_unique_block_coord(id); - // const std::vector> instance_map = + // const auto unique_block_coord = + // device_rr_gsb.get_cbx_unique_block_coord(id); const + // std::vector> instance_map = // device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); // auto unique_block = unique_blocks[id]; @@ -275,13 +282,13 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, // } // } - // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); // id < device_rr_gsb.get_num_sb_unique_module() + // device_rr_gsb.get_num_cb_unique_module(CHANY); // ++id) { - // const auto unique_block_coord = device_rr_gsb.get_cby_unique_block_coord(id); - // const std::vector> instance_map = + // const auto unique_block_coord = + // device_rr_gsb.get_cby_unique_block_coord(id); const + // std::vector> instance_map = // device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); // auto unique_block = unique_blocks[id]; @@ -301,7 +308,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, // } // } // } - // writeMessageToFile(fname, &builder); + writeMessageToFile(fname, &builder); return 0; } diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index ca3433648..8294afe6b 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -35,5 +35,10 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); + +// int write_bin_atom_block(const std::vector>& instance_map, +// const vtr::Point& unique_block_coord, +// const ::uniqueblockcap::BlockType type, +// uniqueblockcap::UniqueBlockPacked::Builder &root); } // namespace openfpga #endif From ef18d04a3a3b6f6f3e1a068671fedf86a9e417a6 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 27 Sep 2024 17:21:24 +0800 Subject: [PATCH 05/23] write bin function works now --- libs/libopenfpgacapnproto/README.md | 44 ++--- openfpga/src/annotation/device_rr_gsb.cpp | 12 +- .../annotation/write_xml_unique_blocks.cpp | 185 +++++++----------- .../src/annotation/write_xml_unique_blocks.h | 9 +- 4 files changed, 106 insertions(+), 144 deletions(-) diff --git a/libs/libopenfpgacapnproto/README.md b/libs/libopenfpgacapnproto/README.md index 38187e075..f3716fc7b 100644 --- a/libs/libopenfpgacapnproto/README.md +++ b/libs/libopenfpgacapnproto/README.md @@ -1,12 +1,10 @@ -Capnproto usage in VTR +Capnproto usage in Openfpga ====================== Capnproto is a data serialization framework designed for portabliity and speed. -In VPR, capnproto is used to provide binary formats for internal data +In Openfpga, capnproto is used to provide binary formats for internal data structures that can be computed once, and used many times. Specific examples: - - rrgraph - - Router lookahead data - - Place matrix delay estimates + - preload unique blocks What is capnproto? ================== @@ -29,56 +27,48 @@ These source and header files combined with the capnproto C++ library, enables C++ code to read and write the messages matching a particular schema. The C++ library API can be found here: https://capnproto.org/cxx.html -Contents of libvtrcapnproto +Contents of libopenfpgacapnproto =========================== -libvtrcapnproto should contain two elements: - - Utilities for working capnproto messages in VTR - - Generate source and header files of all capnproto messages used in VTR +libopenfpgacapnproto should contain two elements: + - Utilities for working capnproto messages in Openfpga + - Generate source and header files of all capnproto messages used in Openfpga I/O Utilities ------------- Capnproto does not provide IO support, instead it works from arrays (or file -descriptors). To avoid re-writing this code, libvtrcapnproto provides two +descriptors). To avoid re-writing this code, libopenfpgacapnproto provides two utilities that should be used whenever reading or writing capnproto message to -disk: +disk. These two files are copied : - `serdes_utils.h` provides the writeMessageToFile function - Writes a capnproto message to disk. - `mmap_file.h` provides MmapFile object - Maps a capnproto message from the disk as a flat array. -NdMatrix Utilities ------------------- - -A common datatype which appears in many data structures that VPR might want to -serialize is the generic type `vtr::NdMatrix`. `ndmatrix_serdes.h` provides -generic functions ToNdMatrix and FromNdMatrix, which can be used to generically -convert between the provideid capnproto message `Matrix` and `vtr::NdMatrix`. - Capnproto schemas ----------------- -libvtrcapnproto should contain all capnproto schema definitions used within +libopenfpgacapnproto should contain all capnproto schema definitions used within VTR. To add a new schema: -1. Add the schema to git in `libs/libvtrcapnproto/` +1. Add the schema to git in `libs/libopenfpgacapnproto/` 2. Add the schema file name to `capnp_generate_cpp` invocation in - `libs/libvtrcapnproto/CMakeLists.txt`. + `libs/libopenfpgacapnproto/CMakeLists.txt`. The schema will be available in the header file `schema filename>.h`. The actual header file will appear in the CMake build directory -`libs/libvtrcapnproto` after `libvtrcapnproto` has been rebuilt. +`libs/libopenfpgacapnproto` after `libopenfpgacapnproto` has been rebuilt. Writing capnproto binary files to text ====================================== The `capnp` tool (found in the CMake build directiory -`libs/EXTERNAL/capnproto/c++/src/capnp`) can be used to convert from a binary +`/vtr-verilog-to-routing/libs/EXTERNAL/capnproto/c++/src/capnp`) can be used to convert from a binary capnp message to a textual form. -Example converting VprOverrideDelayModel from binary to text: +Example converting UniqueBlockCompactInfo from binary to text: ``` -capnp convert binary:text place_delay_model.capnp VprOverrideDelayModel \ - < place_delay.bin > place_delay.txt +capnp convert binary:text unique_blocks_uxsdcxx.capnp UniqueBlockCompactInfo \ + < test.bin > test.txt ``` diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 2886b378a..388b6b945 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -116,7 +116,9 @@ std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( sb_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - instance_map.push_back(instance_coord); + if (instance_coord != unique_block_coord){ + instance_map.push_back(instance_coord); + } } } } @@ -144,7 +146,9 @@ DeviceRRGSB::get_cbx_unique_block_instance_coord( cbx_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - instance_map.push_back(instance_coord); + if (instance_coord != unique_block_coord){ + instance_map.push_back(instance_coord); + } } } } @@ -172,7 +176,9 @@ DeviceRRGSB::get_cby_unique_block_instance_coord( cby_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - instance_map.push_back(instance_coord); + if (instance_coord != unique_block_coord){ + instance_map.push_back(instance_coord); + } } } } diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index a92fc31b0..146c44ff5 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -50,18 +50,14 @@ int write_xml_atom_block(std::fstream& fp, << "\n"; for (const auto& instance_info : instance_map) { - if (instance_info.x() == unique_block_coord.x() && - instance_info.y() == unique_block_coord.y()) { - ; - } else { - openfpga::write_tab_to_file(fp, 2); - fp << "" - << "\n"; - } + fp << "/>" + << "\n"; + } openfpga::write_tab_to_file(fp, 1); fp << "" @@ -190,126 +186,97 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, return CMD_EXEC_SUCCESS; } -// int write_bin_atom_block(const std::vector>& instance_map, -// const vtr::Point& unique_block_coord, -// const uniqueblockcap::BlockType type, -// uniqueblockcap::UniqueBlockPacked::Builder &root) { -// -// auto block_info = root.initBlockInfo(); -// block_info.setX(unique_block_coord.x()); -// block_info.setY(unique_block_coord.y()); -// block_info.setType(type); -// auto instance_list = root.initInstanceList(instance_map.size()); -// for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { -// if (instance_map[instance_id].x() == unique_block_coord.x() && -// instance_map[instance_id].y() == unique_block_coord.y()) { -// ; -// } else { -// auto instance = instance_list[instance_id]; -// instance.setX(instance_map[instance_id].x()); -// instance.setY(instance_map[instance_id].y()); -// } -// } -// return openfpga::CMD_EXEC_SUCCESS; -// } +/* write each unique block (including a single unique block info and its mirror + * instances' info)into capnp builder */ +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const uniqueblockcap::BlockType type, + uniqueblockcap::UniqueBlockPacked::Builder& root) { + auto block_info = root.initBlockInfo(); + block_info.setX(unique_block_coord.x()); + block_info.setY(unique_block_coord.y()); + block_info.setType(type); + if (instance_map.size() > 0) { + auto instance_list = root.initInstanceList(instance_map.size()); + for (size_t instance_id = 0; instance_id < instance_map.size(); + instance_id++) { + auto instance = instance_list[instance_id]; + instance.setX(instance_map[instance_id].x()); + instance.setY(instance_map[instance_id].y()); + } + } + return openfpga::CMD_EXEC_SUCCESS; +} +/* Top-level function to write bin file of unique blocks */ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { ::capnp::MallocMessageBuilder builder; auto unique_blocks = builder.initRoot(); - void* context; int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); auto block_list = unique_blocks.initAtomInfo(num_unique_blocks); + /*write switch blocks into bin file */ for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); const std::vector> instance_map = device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); - + std::cout << "what is instance size: " << instance_map.size() << std::endl; auto unique_block = block_list[id]; - - auto block_info = unique_block.initBlockInfo(); - block_info.setX(unique_block_coord.x()); - block_info.setY(unique_block_coord.y()); - block_info.setType(uniqueblockcap::BlockType::SB); - auto instance_list = unique_block.initInstanceList(instance_map.size()); - for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { - if (instance_map[instance_id].x() == unique_block_coord.x() && - instance_map[instance_id].y() == unique_block_coord.y()) { - ; - } else { - auto instance = instance_list[instance_id]; - instance.setX(instance_map[instance_id].x()); - instance.setY(instance_map[instance_id].y()); - } + int status_code = + write_bin_atom_block(instance_map, unique_block_coord, + uniqueblockcap::BlockType::SB, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; } - - // int status_code = write_bin_atom_block(instance_map, unique_block_coord, - // uniqueblockcap::BlockType::SB, unique_block); - // if (status_code != 0) { - // VTR_LOG_ERROR("write cbx unique blocks into xml file failed!"); - // return CMD_EXEC_FATAL_ERROR; - // } } - // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); - // id < device_rr_gsb.get_num_sb_unique_module() + - // device_rr_gsb.get_num_cb_unique_module(CHANX); - // ++id) { - // const auto unique_block_coord = - // device_rr_gsb.get_cbx_unique_block_coord(id); const - // std::vector> instance_map = - // device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + /*write cbx blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cbx_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module(); + auto unique_block = block_list[block_id]; + int status_code = + write_bin_atom_block(instance_map, unique_block_coord, + uniqueblockcap::BlockType::CBX, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } - // auto unique_block = unique_blocks[id]; - // auto block_info = unique_block.initBlockInfo(); - // block_info.setX(unique_block_coord.x()); - // block_info.setY(unique_block_coord.y()); - // block_info.setType(SB); - // auto instance_list = unique_block.initInstanceList(instance_map.size()); - // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { - // if (instance_map[instance_id].x() == unique_block_coord.x() && - // instance_map[instance_id].y() == unique_block_coord.y()) { - // ; - // } else { - // auto instance = instance_list[instance_id]; - // instance.setX(instance_map[instance_id].x()); - // instance.setY(instance_map[instance_id].y()); - // } - // } - // } + /*write cby blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cby_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX); + auto unique_block = block_list[block_id]; + int status_code = + write_bin_atom_block(instance_map, unique_block_coord, + uniqueblockcap::BlockType::CBY, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } - // for (size_t id = device_rr_gsb.get_num_sb_unique_module(); - // id < device_rr_gsb.get_num_sb_unique_module() + - // device_rr_gsb.get_num_cb_unique_module(CHANY); - // ++id) { - // const auto unique_block_coord = - // device_rr_gsb.get_cby_unique_block_coord(id); const - // std::vector> instance_map = - // device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); - - // auto unique_block = unique_blocks[id]; - // auto block_info = unique_block.initBlockInfo(); - // block_info.setX(unique_block_coord.x()); - // block_info.setY(unique_block_coord.y()); - // block_info.setType(SB); - // auto instance_list = unique_block.initInstanceList(instance_map.size()); - // for (size_t instance_id = 0; instance_id < instance_map; instance_id++) { - // if (instance_map[instance_id].x() == unique_block_coord.x() && - // instance_map[instance_id].y() == unique_block_coord.y()) { - // ; - // } else { - // auto instance = instance_list[instance_id]; - // instance.setX(instance_map[instance_id].x()); - // instance.setY(instance_map[instance_id].y()); - // } - // } - // } writeMessageToFile(fname, &builder); - return 0; + if (verbose_output) { + report_unique_module_status_write(device_rr_gsb, true); + } + return openfpga::CMD_EXEC_SUCCESS; } } // namespace openfpga diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index 8294afe6b..6b56c67ff 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -35,10 +35,9 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); - -// int write_bin_atom_block(const std::vector>& instance_map, -// const vtr::Point& unique_block_coord, -// const ::uniqueblockcap::BlockType type, -// uniqueblockcap::UniqueBlockPacked::Builder &root); +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const uniqueblockcap::BlockType type, + uniqueblockcap::UniqueBlockPacked::Builder& root); } // namespace openfpga #endif From 1d6f9901bb8d2ac80cdde78231171f5600fbb912 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 27 Sep 2024 17:23:17 +0800 Subject: [PATCH 06/23] renamed file --- .../{write_xml_unique_blocks.cpp => write_unique_blocks.cpp} | 2 +- .../{write_xml_unique_blocks.h => write_unique_blocks.h} | 0 openfpga/src/base/openfpga_build_fabric_template.h | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename openfpga/src/annotation/{write_xml_unique_blocks.cpp => write_unique_blocks.cpp} (99%) rename openfpga/src/annotation/{write_xml_unique_blocks.h => write_unique_blocks.h} (100%) diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp similarity index 99% rename from openfpga/src/annotation/write_xml_unique_blocks.cpp rename to openfpga/src/annotation/write_unique_blocks.cpp index 146c44ff5..9a6a5cf4e 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -19,7 +19,7 @@ #include "read_xml_util.h" #include "rr_gsb.h" #include "unique_blocks_uxsdcxx.capnp.h" -#include "write_xml_unique_blocks.h" +#include "write_unique_blocks.h" #include "write_xml_utils.h" /******************************************************************** diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_unique_blocks.h similarity index 100% rename from openfpga/src/annotation/write_xml_unique_blocks.h rename to openfpga/src/annotation/write_unique_blocks.h diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 06d157ed5..8bd22431c 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -27,7 +27,7 @@ #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" -#include "write_xml_unique_blocks.h" +#include "write_unique_blocks.h" /* begin namespace openfpga */ namespace openfpga { From 59f1e4adc9b51f9b78cb4df00ce200aa1f324ca7 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 27 Sep 2024 18:28:53 +0800 Subject: [PATCH 07/23] add read bin (with bugs) --- .../src/annotation/read_xml_unique_blocks.cpp | 78 ++++++++++++++++++- .../src/annotation/read_xml_unique_blocks.h | 9 ++- .../src/annotation/write_unique_blocks.cpp | 1 - 3 files changed, 83 insertions(+), 5 deletions(-) diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index e451328ff..e9e72cd90 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -12,10 +12,12 @@ #include "arch_error.h" #include "command_exit_codes.h" #include "device_rr_gsb_utils.h" +#include "mmap_file.h" #include "openfpga_digest.h" #include "read_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" #include "write_xml_utils.h" /******************************************************************** @@ -155,9 +157,79 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, } } -int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, - bool verbose_output) { - return 0; +/*read the instances' coordinate of a unique block from a bin file*/ +std::vector> read_bin_unique_instance_coords( + const uniqueblockcap::BlockInfo::Reader& unique_block) { + std::vector> instance_coords; + if (unique_block.hasInstanceList()) { + auto instance_list = unique_block.getInstanceList(); + for (auto instance : instance_list) { + int instance_x = instance.getX(); + int instance_y = instance.getY(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + return instance_coords; } +/*read the unique block coordinate from a bin file */ +vtr::Point read_bin_unique_block_coord( + const uniqueblockcap::BlockInfo::Reader& unique_block) { + auto block_info = unique_block.getBlockInfo(); + std::string type = block_info.getType().Cstr(); + int block_x = block_info.getX(); + int block_y = block_info.getY(); + vtr::Point block_coordinate(block_x, block_y); + return block_coordinate; +} + +/*top-level function to read unique blocks from bin file*/ +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + /* clear unique modules & reserve memory to relavant vectors */ + device_rr_gsb.clear_unique_modules(); + // vtr::Point grid_coord(rr_gsb_.size()); + device_rr_gsb.reserve_unique_modules(); + MmapFile f(file_name); + ::uniqueblockcap::FlatArrayMessageReader reader(f.getData()); + auto root = reader.getRoot(); + if (root.hasAtomInfo()) { + auto block_list = root.getAtomInfo(); + for (auto unqiue_block : block_list) { + auto block_info = unique_block.getBlockInfo(); + std::string type = block_info.getType().Cstr(); + int block_x = block_info.getX(); + int block_y = block_info.getY(); + vtr::Point block_coordinate(block_x, block_y); + if (unique_block.hasInstanceList()) { + auto instance_list = unique_block.getInstanceList(); + std::vector> instance_coords; + for (auto instance : instance_list) { + int instance_x = instance.getX(); + int instance_y = instance.getY(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ + if (type == "sb") { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == "cby") { + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); + } else if (type == "cbx") { + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); + } + } + } + device_rr_gsb.build_gsb_unique_module(); + if (verbose_output) { + report_unique_module_status_read(device_rr_gsb, true); + } + return CMD_EXEC_SUCCESS; +} } // namespace openfpga diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index d5a0dcca8..8c6f2103d 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -36,7 +36,14 @@ void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); +std::vector> read_bin_unique_instance_coords( + const uniqueblockcap::BlockInfo::Reader& unique_block); + +vtr::Point read_bin_unique_block_coord( + const uniqueblockcap::BlockInfo::Reader& unique_block); + int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, - bool verbose_output); + bool verbose_output) } // namespace openfpga + #endif diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp index 9a6a5cf4e..370ea4e90 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -224,7 +224,6 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); const std::vector> instance_map = device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); - std::cout << "what is instance size: " << instance_map.size() << std::endl; auto unique_block = block_list[id]; int status_code = write_bin_atom_block(instance_map, unique_block_coord, From ed381692a77b47999dd2054ea5c2e32485cf1912 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 27 Sep 2024 18:41:30 +0800 Subject: [PATCH 08/23] read bin format mod (with bug) --- libs/libopenfpgacapnproto/mmap_file.cpp | 46 +++++++++---------- libs/libopenfpgacapnproto/mmap_file.h | 13 +++--- libs/libopenfpgacapnproto/serdes_utils.cpp | 27 +++++------ libs/libopenfpgacapnproto/serdes_utils.h | 11 +++-- openfpga/src/annotation/device_rr_gsb.cpp | 6 +-- .../src/annotation/read_xml_unique_blocks.cpp | 19 ++------ .../src/annotation/read_xml_unique_blocks.h | 2 +- .../src/annotation/write_unique_blocks.cpp | 3 +- .../src/base/openfpga_build_fabric_template.h | 2 +- 9 files changed, 60 insertions(+), 69 deletions(-) diff --git a/libs/libopenfpgacapnproto/mmap_file.cpp b/libs/libopenfpgacapnproto/mmap_file.cpp index e77c56366..caa697ef7 100644 --- a/libs/libopenfpgacapnproto/mmap_file.cpp +++ b/libs/libopenfpgacapnproto/mmap_file.cpp @@ -1,39 +1,39 @@ #include "mmap_file.h" -#include "vtr_error.h" -#include "vtr_util.h" #include #include + +#include "vtr_error.h" +#include "vtr_util.h" #ifndef _WIN32 - #include +#include #endif #include #include "kj/filesystem.h" -MmapFile::MmapFile(const std::string& file) - : size_(0) { - try { - auto fs = kj::newDiskFilesystem(); - auto path = fs->getCurrentPath().evalNative(file); +MmapFile::MmapFile(const std::string& file) : size_(0) { + try { + auto fs = kj::newDiskFilesystem(); + auto path = fs->getCurrentPath().evalNative(file); - const auto& dir = fs->getRoot(); - auto stat = dir.lstat(path); - auto f = dir.openFile(path); - size_ = stat.size; - data_ = f->mmap(0, stat.size); - } catch (kj::Exception& e) { - throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); - } + const auto& dir = fs->getRoot(); + auto stat = dir.lstat(path); + auto f = dir.openFile(path); + size_ = stat.size; + data_ = f->mmap(0, stat.size); + } catch (kj::Exception& e) { + throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); + } } const kj::ArrayPtr MmapFile::getData() const { - if ((size_ % sizeof(::capnp::word)) != 0) { - throw vtr::VtrError( - vtr::string_fmt("size_ %d is not a multiple of capnp::word", size_), - __FILE__, __LINE__); - } + if ((size_ % sizeof(::capnp::word)) != 0) { + throw vtr::VtrError( + vtr::string_fmt("size_ %d is not a multiple of capnp::word", size_), + __FILE__, __LINE__); + } - return kj::arrayPtr(reinterpret_cast(data_.begin()), - size_ / sizeof(::capnp::word)); + return kj::arrayPtr(reinterpret_cast(data_.begin()), + size_ / sizeof(::capnp::word)); } diff --git a/libs/libopenfpgacapnproto/mmap_file.h b/libs/libopenfpgacapnproto/mmap_file.h index ee1a93e83..4b3d0ff25 100644 --- a/libs/libopenfpgacapnproto/mmap_file.h +++ b/libs/libopenfpgacapnproto/mmap_file.h @@ -2,18 +2,19 @@ #define MMAP_FILE_H_ #include + #include "capnp/message.h" #include "kj/array.h" // Platform independent mmap, useful for reading large capnp's. class MmapFile { - public: - explicit MmapFile(const std::string& file); - const kj::ArrayPtr getData() const; + public: + explicit MmapFile(const std::string& file); + const kj::ArrayPtr getData() const; - private: - size_t size_; - kj::Array data_; + private: + size_t size_; + kj::Array data_; }; #endif /* MMAP_FILE_H_ */ diff --git a/libs/libopenfpgacapnproto/serdes_utils.cpp b/libs/libopenfpgacapnproto/serdes_utils.cpp index 2201fa584..88d84a455 100644 --- a/libs/libopenfpgacapnproto/serdes_utils.cpp +++ b/libs/libopenfpgacapnproto/serdes_utils.cpp @@ -3,20 +3,21 @@ #include #include -#include "vtr_error.h" #include "kj/filesystem.h" +#include "vtr_error.h" -void writeMessageToFile(const std::string& file, ::capnp::MessageBuilder* builder) { - try { - auto fs = kj::newDiskFilesystem(); - auto path = fs->getCurrentPath().evalNative(file); +void writeMessageToFile(const std::string& file, + ::capnp::MessageBuilder* builder) { + try { + auto fs = kj::newDiskFilesystem(); + auto path = fs->getCurrentPath().evalNative(file); - const auto& dir = fs->getRoot(); - auto f = dir.openFile(path, kj::WriteMode::CREATE | kj::WriteMode::MODIFY); - f->truncate(0); - auto f_app = kj::newFileAppender(std::move(f)); - capnp::writeMessage(*f_app, *builder); - } catch (kj::Exception& e) { - throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); - } + const auto& dir = fs->getRoot(); + auto f = dir.openFile(path, kj::WriteMode::CREATE | kj::WriteMode::MODIFY); + f->truncate(0); + auto f_app = kj::newFileAppender(std::move(f)); + capnp::writeMessage(*f_app, *builder); + } catch (kj::Exception& e) { + throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); + } } diff --git a/libs/libopenfpgacapnproto/serdes_utils.h b/libs/libopenfpgacapnproto/serdes_utils.h index 723a14772..0c961d314 100644 --- a/libs/libopenfpgacapnproto/serdes_utils.h +++ b/libs/libopenfpgacapnproto/serdes_utils.h @@ -3,18 +3,19 @@ #include #include + #include "capnp/serialize.h" // Platform indepedent way to file message to a file on disk. void writeMessageToFile(const std::string& file, - ::capnp::MessageBuilder* builder); + ::capnp::MessageBuilder* builder); inline ::capnp::ReaderOptions default_large_capnp_opts() { - ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); + ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); - /* Remove traversal limit */ - opts.traversalLimitInWords = std::numeric_limits::max(); - return opts; + /* Remove traversal limit */ + opts.traversalLimitInWords = std::numeric_limits::max(); + return opts; } #endif /* SERDES_UTILS_H_ */ diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 388b6b945..86d6cfdc4 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -116,7 +116,7 @@ std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( sb_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - if (instance_coord != unique_block_coord){ + if (instance_coord != unique_block_coord) { instance_map.push_back(instance_coord); } } @@ -146,7 +146,7 @@ DeviceRRGSB::get_cbx_unique_block_instance_coord( cbx_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - if (instance_coord != unique_block_coord){ + if (instance_coord != unique_block_coord) { instance_map.push_back(instance_coord); } } @@ -176,7 +176,7 @@ DeviceRRGSB::get_cby_unique_block_instance_coord( cby_unique_module_id_[location_x][location_y]; if (unique_module_id_instance == unique_module_id) { vtr::Point instance_coord(location_x, location_y); - if (instance_coord != unique_block_coord){ + if (instance_coord != unique_block_coord) { instance_map.push_back(instance_coord); } } diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index e9e72cd90..92d47d2ff 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -197,21 +197,10 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, if (root.hasAtomInfo()) { auto block_list = root.getAtomInfo(); for (auto unqiue_block : block_list) { - auto block_info = unique_block.getBlockInfo(); - std::string type = block_info.getType().Cstr(); - int block_x = block_info.getX(); - int block_y = block_info.getY(); - vtr::Point block_coordinate(block_x, block_y); - if (unique_block.hasInstanceList()) { - auto instance_list = unique_block.getInstanceList(); - std::vector> instance_coords; - for (auto instance : instance_list) { - int instance_x = instance.getX(); - int instance_y = instance.getY(); - vtr::Point instance_coordinate(instance_x, instance_y); - instance_coords.push_back(instance_coordinate); - } - } + vtr::Point block_coordinate = + read_bin_unique_block_coord(unique_block); + std::vector> instance_coords = + read_bin_unique_instance_coords(unique_block); /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ if (type == "sb") { diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index 8c6f2103d..b38d7c373 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -43,7 +43,7 @@ vtr::Point read_bin_unique_block_coord( const uniqueblockcap::BlockInfo::Reader& unique_block); int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, - bool verbose_output) + bool verbose_output); } // namespace openfpga #endif diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp index 370ea4e90..a7d48eb50 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -56,8 +56,7 @@ int write_xml_atom_block(std::fstream& fp, write_xml_attribute(fp, "y", instance_info.y()); fp << "/>" - << "\n"; - + << "\n"; } openfpga::write_tab_to_file(fp, 1); fp << "" diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 8bd22431c..8ce8e152e 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -25,9 +25,9 @@ #include "report_reference.h" #include "vtr_log.h" #include "vtr_time.h" +#include "write_unique_blocks.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" -#include "write_unique_blocks.h" /* begin namespace openfpga */ namespace openfpga { From 08ec3760e4a84cc9ddcf77b1ee1e9cd510fdc44e Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 10:46:50 +0800 Subject: [PATCH 09/23] mod read bin --- .../src/annotation/read_xml_unique_blocks.cpp | 20 +++++++++---------- .../src/annotation/read_xml_unique_blocks.h | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 92d47d2ff..87cb6873f 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -111,7 +111,6 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); - // vtr::Point grid_coord(rr_gsb_.size()); device_rr_gsb.reserve_unique_modules(); /* load unique blocks xml file and set up device_rr_gdb */ @@ -159,7 +158,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /*read the instances' coordinate of a unique block from a bin file*/ std::vector> read_bin_unique_instance_coords( - const uniqueblockcap::BlockInfo::Reader& unique_block) { + const uniqueblockcap::UniqueBlockPacked::Reader& unique_block) { std::vector> instance_coords; if (unique_block.hasInstanceList()) { auto instance_list = unique_block.getInstanceList(); @@ -175,11 +174,12 @@ std::vector> read_bin_unique_instance_coords( /*read the unique block coordinate from a bin file */ vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::BlockInfo::Reader& unique_block) { + const uniqueblockcap::BlockInfo::Reader& unique_block, std::string type) { auto block_info = unique_block.getBlockInfo(); std::string type = block_info.getType().Cstr(); int block_x = block_info.getX(); int block_y = block_info.getY(); + type = block_info.getType(); vtr::Point block_coordinate(block_x, block_y); return block_coordinate; } @@ -189,27 +189,27 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output) { /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); - // vtr::Point grid_coord(rr_gsb_.size()); device_rr_gsb.reserve_unique_modules(); MmapFile f(file_name); - ::uniqueblockcap::FlatArrayMessageReader reader(f.getData()); + ::capnp::FlatArrayMessageReader reader(f.getData()); auto root = reader.getRoot(); if (root.hasAtomInfo()) { auto block_list = root.getAtomInfo(); for (auto unqiue_block : block_list) { + std::string type; vtr::Point block_coordinate = - read_bin_unique_block_coord(unique_block); + read_bin_unique_block_coord(unique_block, type); /*get block coordinate and type*/ std::vector> instance_coords = - read_bin_unique_instance_coords(unique_block); + read_bin_unique_instance_coords(unique_block); /* get a list of instance coordinates*/ /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ - if (type == "sb") { + if (type == uniqueblockcap::BlockType::SB) { device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); - } else if (type == "cby") { + } else if (type == uniqueblockcap::BlockType::CBY) { device_rr_gsb.preload_unique_cby_module(block_coordinate, instance_coords); - } else if (type == "cbx") { + } else if (type == uniqueblockcap::BlockType::CBX) { device_rr_gsb.preload_unique_cbx_module(block_coordinate, instance_coords); } diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index b38d7c373..dd27a59ed 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -40,7 +40,7 @@ std::vector> read_bin_unique_instance_coords( const uniqueblockcap::BlockInfo::Reader& unique_block); vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::BlockInfo::Reader& unique_block); + const uniqueblockcap::BlockInfo::Reader& unique_block, std::string& type); int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); From 87ca9f3006bc45026de4c1e03f2d465ab8eaff92 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 11:09:01 +0800 Subject: [PATCH 10/23] add three testcases to test bin read and write --- ...e_blocks_full_flow_example_script.openfpga | 79 ++++++++++++++++ ...e_xml_uniqueblocks_example_script.openfpga | 82 +++++++++++++++++ ...read_unique_blocks_example_script.openfpga | 2 +- ...e_blocks_full_flow_example_script.openfpga | 2 +- ...e_blocks_full_flow_example_script.openfpga | 80 ++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 3 + .../read_unique_blocks_bin/config/task.conf | 42 +++++++++ .../config/tile_config.xml | 1 + .../read_unique_block.xml | 92 +++++++++++++++++++ .../config/task.conf | 42 +++++++++ .../config/tile_config.xml | 1 + .../read_unique_block.xml | 92 +++++++++++++++++++ .../config/task.conf | 41 +++++++++ .../config/tile_config.xml | 1 + 14 files changed, 558 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml diff --git a/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..62db921b2 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided xml file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS_BIN} --verbose --type bin + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga new file mode 100644 index 000000000..843c36ae7 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga @@ -0,0 +1,82 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided xml file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS_BIN} --verbose --type bin + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks xml file +write_unique_blocks --file ./write_unique_block.xml --verbose --type xml + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga index 91e717186..a311e9870 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga @@ -21,7 +21,7 @@ read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing #--verbose +build_fabric #--verbose #write unique blocks xml file write_unique_blocks --file ./write_unique_block.xml --verbose --type xml diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga index a6f980f92..649999219 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga @@ -27,7 +27,7 @@ read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..1c07f8b7c --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,80 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks xml file +write_unique_blocks --file ./write_unique_block.bin --verbose --type bin + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index e5dd8fa57..0c7de95d6 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -24,6 +24,9 @@ run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@ run-task basic_tests/preload_unique_blocks/read_write_unique_blocks $@ +run-task basic_tests/preload_unique_blocks/read_write_unique_blocks_bin $@ +run-task basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_unique_blocks_bin $@ echo -e "Testing testbenches using fpga core wrapper" diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf new file mode 100644 index 000000000..95ac26b89 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf new file mode 100644 index 000000000..f3a2f2299 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..bc6bcd521 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + From 6864159f31586e88c7040fd4aa9a4da1314d3b4b Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 11:20:46 +0800 Subject: [PATCH 11/23] modified testcases --- .../read_unique_blocks_bin/config/task.conf | 2 +- .../read_write_unique_blocks_bin/config/task.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf index 95ac26b89..41a49a326 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin +read_unique_blocks_bin =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf index f3a2f2299..f942d71fc 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +read_unique_blocks_bin =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 From bddf693d7b2a3b9fec4aa62cff828562aefa4559 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 12:22:02 +0800 Subject: [PATCH 12/23] read bin ready --- .../src/annotation/read_xml_unique_blocks.cpp | 19 ++++++++++++------- .../src/annotation/read_xml_unique_blocks.h | 5 +++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 87cb6873f..61f848e07 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -1,3 +1,7 @@ +#include +#include +#include + #include /* Headers from pugi XML library */ #include "pugixml.hpp" @@ -174,9 +178,9 @@ std::vector> read_bin_unique_instance_coords( /*read the unique block coordinate from a bin file */ vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::BlockInfo::Reader& unique_block, std::string type) { + const uniqueblockcap::UniqueBlockPacked::Reader& unique_block, + uniqueblockcap::BlockType& type) { auto block_info = unique_block.getBlockInfo(); - std::string type = block_info.getType().Cstr(); int block_x = block_info.getX(); int block_y = block_info.getY(); type = block_info.getType(); @@ -195,12 +199,13 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, auto root = reader.getRoot(); if (root.hasAtomInfo()) { auto block_list = root.getAtomInfo(); - for (auto unqiue_block : block_list) { - std::string type; - vtr::Point block_coordinate = - read_bin_unique_block_coord(unique_block, type); /*get block coordinate and type*/ + for (auto unique_block : block_list) { + uniqueblockcap::BlockType type; + vtr::Point block_coordinate = read_bin_unique_block_coord( + unique_block, type); /*get block coordinate and type*/ std::vector> instance_coords = - read_bin_unique_instance_coords(unique_block); /* get a list of instance coordinates*/ + read_bin_unique_instance_coords( + unique_block); /* get a list of instance coordinates*/ /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ if (type == uniqueblockcap::BlockType::SB) { diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index dd27a59ed..84f81502b 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -37,10 +37,11 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); std::vector> read_bin_unique_instance_coords( - const uniqueblockcap::BlockInfo::Reader& unique_block); + const uniqueblockcap::UniqueBlockPacked::Reader& unique_block); vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::BlockInfo::Reader& unique_block, std::string& type); + const uniqueblockcap::UniqueBlockPacked::Reader& unique_block, + uniqueblockcap::BlockType& type); int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); From 20238c1a2d928d7e8fc595a5c87efb3c1154ccb6 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 12:30:39 +0800 Subject: [PATCH 13/23] modified testcase --- .../read_unique_block.bin | Bin 0 -> 1080 bytes .../read_unique_block.xml | 92 ------------------ .../read_unique_block.bin | Bin 0 -> 1080 bytes .../read_unique_block.xml | 92 ------------------ 4 files changed, 184 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin delete mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin delete mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin new file mode 100644 index 0000000000000000000000000000000000000000..9c80bdceb57ad4e81e93403fae579dc951798997 GIT binary patch literal 1080 zcmZ{fp;7}u5JWctfxu%@#o=S{cq|5;pTOW^g2M187#s$N$)8|QSo-blyBYyg)z{lS zJ+rs1we}RuwQ8#zeuA5BtlL9)-Ouw!{TO)>?1S1@AL7%09{rc_ZSXquTbTa)(4k)H zk0|<|LEW!D#%JHx=zoWI!6pwNe-*wAZ->4PlfN7KK1_Z;^dU^X-W9p%w0oW9>)Gr{ zJkO_dtZQ>v&Y5F|LX$H)6>ZP`Wbgz&z&E4ktp8K*$0G-mGn3<@{U7IQ*1PcPtTXJH zf~xV<+)1&AayRGdp(*B^-4^W|{U0)T0w3U;(c?~h?}q77`kc>)W~Uigkfr3Qobf4U pDfcsL{;wWc`U3smyUDPRJ)B|To9T0=uLleNM^0;bx4Yc|gJ1sz6l?$h literal 0 HcmV?d00001 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml deleted file mode 100644 index 12570d65e..000000000 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.xml +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin new file mode 100644 index 0000000000000000000000000000000000000000..9c80bdceb57ad4e81e93403fae579dc951798997 GIT binary patch literal 1080 zcmZ{fp;7}u5JWctfxu%@#o=S{cq|5;pTOW^g2M187#s$N$)8|QSo-blyBYyg)z{lS zJ+rs1we}RuwQ8#zeuA5BtlL9)-Ouw!{TO)>?1S1@AL7%09{rc_ZSXquTbTa)(4k)H zk0|<|LEW!D#%JHx=zoWI!6pwNe-*wAZ->4PlfN7KK1_Z;^dU^X-W9p%w0oW9>)Gr{ zJkO_dtZQ>v&Y5F|LX$H)6>ZP`Wbgz&z&E4ktp8K*$0G-mGn3<@{U7IQ*1PcPtTXJH zf~xV<+)1&AayRGdp(*B^-4^W|{U0)T0w3U;(c?~h?}q77`kc>)W~Uigkfr3Qobf4U pDfcsL{;wWc`U3smyUDPRJ)B|To9T0=uLleNM^0;bx4Yc|gJ1sz6l?$h literal 0 HcmV?d00001 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml deleted file mode 100644 index 12570d65e..000000000 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.xml +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 7d9a677534c13048302290622d4e1a63bc9dca85 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 13:17:13 +0800 Subject: [PATCH 14/23] changed file name --- .../{read_xml_unique_blocks.cpp => read_unique_blocks.cpp} | 2 +- .../{read_xml_unique_blocks.h => read_unique_blocks.h} | 0 openfpga/src/base/openfpga_build_fabric_template.h | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename openfpga/src/annotation/{read_xml_unique_blocks.cpp => read_unique_blocks.cpp} (99%) rename openfpga/src/annotation/{read_xml_unique_blocks.h => read_unique_blocks.h} (100%) diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_unique_blocks.cpp similarity index 99% rename from openfpga/src/annotation/read_xml_unique_blocks.cpp rename to openfpga/src/annotation/read_unique_blocks.cpp index 61f848e07..e3da54ee2 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_unique_blocks.cpp @@ -18,7 +18,7 @@ #include "device_rr_gsb_utils.h" #include "mmap_file.h" #include "openfpga_digest.h" -#include "read_xml_unique_blocks.h" +#include "read_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" #include "unique_blocks_uxsdcxx.capnp.h" diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_unique_blocks.h similarity index 100% rename from openfpga/src/annotation/read_xml_unique_blocks.h rename to openfpga/src/annotation/read_unique_blocks.h diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 8ce8e152e..01416d566 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -20,7 +20,7 @@ #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" -#include "read_xml_unique_blocks.h" +#include "read_unique_blocks.h" #include "rename_modules.h" #include "report_reference.h" #include "vtr_log.h" From bceb160ab8bcbc35153afe5798d5d50ce8dea5d5 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 29 Sep 2024 13:20:49 +0800 Subject: [PATCH 15/23] reformat code --- openfpga/src/base/openfpga_build_fabric_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 01416d566..985bec349 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -16,11 +16,11 @@ #include "fabric_key_writer.h" #include "globals.h" #include "openfpga_naming.h" +#include "read_unique_blocks.h" #include "read_xml_fabric_key.h" #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" -#include "read_unique_blocks.h" #include "rename_modules.h" #include "report_reference.h" #include "vtr_log.h" From 1ba3298dbee0df92474cd5256c99a1be6cc94ff0 Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 8 Oct 2024 11:21:04 +0800 Subject: [PATCH 16/23] add uxsdcxx --- libs/libopenfpgacapnproto/CMakeLists.txt | 24 +++++- .../gen/unique_blocks.xsd | 81 +++++++++++++++++++ ....capnp => unique_blocks_uxsdcxx_pre.capnp} | 0 3 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 libs/libopenfpgacapnproto/gen/unique_blocks.xsd rename libs/libopenfpgacapnproto/gen/{unique_blocks_uxsdcxx.capnp => unique_blocks_uxsdcxx_pre.capnp} (100%) diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt index 401267409..e6041acb3 100644 --- a/libs/libopenfpgacapnproto/CMakeLists.txt +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -35,10 +35,10 @@ find_program(WGET wget REQUIRED) find_package(ZLIB REQUIRED) # Add Java schema -set(JAVA_SCHEMA ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema/capnp/java.capnp) +set(JAVA_SCHEMA ${CMAKE_CURRENT_BINARY_DIR}/schema/capnp/java.capnp) add_custom_command( OUTPUT ${JAVA_SCHEMA} - COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema/capnp/ + COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/schema/capnp/ COMMAND ${WGET} https://raw.githubusercontent.com/capnproto/capnproto-java/master/compiler/src/main/schema/capnp/java.capnp -O ${JAVA_SCHEMA} @@ -46,7 +46,7 @@ add_custom_command( set(CAPNPC_IMPORT_DIRS) -list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/../../vtr-verilog-to-routing/libs/libvtrcapnproto/schema) +list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/schema) set(IC_PROTOS) set(IC_SRCS) @@ -88,3 +88,21 @@ target_link_libraries(libopenfpgacapnproto libopenfpgautil CapnProto::capnp ) + + +add_custom_target( + generate_unique_block_capnp + COMMAND ${CMAKE_COMMAND} -E remove_directory unique_blocks_capnproto_generate + COMMAND ${CMAKE_COMMAND} -E make_directory unique_blocks_capnproto_generate + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate git clone https://github.com/duck2/uxsdcxx + COMMAND python3 -mpip install --user -r unique_blocks_capnproto_generate/uxsdcxx/requirements.txt + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate python3 uxsdcxx/uxsdcxx.py ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd + COMMAND ${CMAKE_COMMAND} -E copy + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h + ${CMAKE_CURRENT_SOURCE_DIR}/gen + COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/gen + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} +) diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd new file mode 100644 index 000000000..ebf4310be --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp similarity index 100% rename from libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp rename to libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp From f0a9ca8b0283a81098e2e2cae3507849e70783f8 Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 8 Oct 2024 16:26:35 +0800 Subject: [PATCH 17/23] add xsd file and modified cmakelist --- libs/libopenfpgacapnproto/CMakeLists.txt | 10 ++- .../gen/unique_blocks.xsd | 75 +++++-------------- .../gen/unique_blocks_uxsdcxx_pre.capnp | 38 ---------- .../src/annotation/read_unique_blocks.cpp | 2 +- .../src/annotation/write_unique_blocks.cpp | 2 +- 5 files changed, 29 insertions(+), 98 deletions(-) delete mode 100644 libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt index e6041acb3..8824d969f 100644 --- a/libs/libopenfpgacapnproto/CMakeLists.txt +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -44,6 +44,10 @@ add_custom_command( -O ${JAVA_SCHEMA} ) +add_custom_target( + get_java_capnp_schema_openfpga + DEPENDS ${JAVA_SCHEMA} +) set(CAPNPC_IMPORT_DIRS) list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/schema) @@ -76,7 +80,9 @@ add_library(libopenfpgacapnproto STATIC add_dependencies(libopenfpgacapnproto - get_java_capnp_schema) + get_java_capnp_schema_openfpga + generate_unique_block_capnp + ) target_include_directories(libopenfpgacapnproto PUBLIC @@ -97,7 +103,7 @@ add_custom_target( COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate git clone https://github.com/duck2/uxsdcxx COMMAND python3 -mpip install --user -r unique_blocks_capnproto_generate/uxsdcxx/requirements.txt COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate python3 uxsdcxx/uxsdcxx.py ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd - COMMAND ${CMAKE_COMMAND} -E copy + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate python3 uxsdcxx/uxsdcap.py ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd index ebf4310be..7d10bcce8 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd +++ b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd @@ -1,30 +1,6 @@ - - - + @@ -34,48 +10,35 @@ - + - - - - - + + + - + - - - - + + - + - - - - - - - + - - - - - - - - - - - - + + + + + + + + + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp deleted file mode 100644 index 1a44cfc9d..000000000 --- a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx_pre.capnp +++ /dev/null @@ -1,38 +0,0 @@ -# This file is generated by uxsdcap 0.1.0. -# https://github.com/duck2/uxsdcxx -# Modify only if your build process doesn't involve regenerating this file. -# -# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 - -@0xa136dddfdd48783b; -using Cxx = import "/capnp/c++.capnp"; -$Cxx.namespace("uniqueblockcap"); - -enum BlockType { - cbx @0; - cby @1; - sb @2; -} - -struct BlockInfo { - type @0: BlockType; - x @1: UInt32; - y @2: UInt32; -} - -struct InstanceInfo { - x @0: UInt32; - y @1: UInt32; -} - - -struct UniqueBlockPacked { - blockInfo @0: BlockInfo; - instanceList @1: List(InstanceInfo); -} - -struct UniqueBlockCompactInfo { - atomInfo @0: List(UniqueBlockPacked); -} diff --git a/openfpga/src/annotation/read_unique_blocks.cpp b/openfpga/src/annotation/read_unique_blocks.cpp index e3da54ee2..8e390279e 100644 --- a/openfpga/src/annotation/read_unique_blocks.cpp +++ b/openfpga/src/annotation/read_unique_blocks.cpp @@ -196,7 +196,7 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, device_rr_gsb.reserve_unique_modules(); MmapFile f(file_name); ::capnp::FlatArrayMessageReader reader(f.getData()); - auto root = reader.getRoot(); + auto root = reader.getRoot(); if (root.hasAtomInfo()) { auto block_list = root.getAtomInfo(); for (auto unique_block : block_list) { diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp index a7d48eb50..18d263714 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -212,7 +212,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { ::capnp::MallocMessageBuilder builder; auto unique_blocks = - builder.initRoot(); + builder.initRoot(); int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); From 9131e743534083cdf5958ded82a71f8f4e4bc12b Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 8 Oct 2024 17:59:20 +0800 Subject: [PATCH 18/23] modified CMakeLists.txt --- libs/libopenfpgacapnproto/CMakeLists.txt | 21 +++---------------- libs/libopenfpgacapnproto/README.md | 2 +- .../gen/unique_blocks.xsd | 2 +- .../gen/unique_blocks_uxsdcxx.capnp | 0 4 files changed, 5 insertions(+), 20 deletions(-) create mode 100644 libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt index 8824d969f..da04f7ecd 100644 --- a/libs/libopenfpgacapnproto/CMakeLists.txt +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -19,6 +19,7 @@ endif() # Create generated headers from capnp schema files # # Each schema used should appear here. + set(CAPNP_DEFS gen/unique_blocks_uxsdcxx.capnp ) @@ -28,8 +29,6 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS ) -set(IC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../vtr-verilog-to-routing/libs/EXTERNAL/libinterchange/interchange) -set(CAPNPC_SRC_PREFIX ${IC_DIR}) find_program(WGET wget REQUIRED) find_package(ZLIB REQUIRED) @@ -52,20 +51,6 @@ add_custom_target( set(CAPNPC_IMPORT_DIRS) list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/schema) -set(IC_PROTOS) -set(IC_SRCS) -set(IC_HDRS) -foreach(PROTO ${IC_PROTOS}) - capnp_generate_cpp( - IC_SRC - IC_HDR - ${IC_DIR}/${PROTO} - ) - list(APPEND IC_SRCS ${IC_SRC}) - list(APPEND IC_HDRS ${IC_HDR}) - list(APPEND CAPNP_DEFS ${IC_DIR}/${PROTO}) -endforeach() - install(FILES ${CAPNP_DEFS} DESTINATION ${CMAKE_INSTALL_DATADIR}/openfpga) @@ -108,7 +93,7 @@ add_custom_target( unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h ${CMAKE_CURRENT_SOURCE_DIR}/gen - COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/gen + COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/../libopenfpgacapnproto/gen DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} -) +) \ No newline at end of file diff --git a/libs/libopenfpgacapnproto/README.md b/libs/libopenfpgacapnproto/README.md index f3716fc7b..cba22314e 100644 --- a/libs/libopenfpgacapnproto/README.md +++ b/libs/libopenfpgacapnproto/README.md @@ -50,7 +50,7 @@ Capnproto schemas ----------------- libopenfpgacapnproto should contain all capnproto schema definitions used within -VTR. To add a new schema: +Openfpga. To add a new schema: 1. Add the schema to git in `libs/libopenfpgacapnproto/` 2. Add the schema file name to `capnp_generate_cpp` invocation in `libs/libopenfpgacapnproto/CMakeLists.txt`. diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd index 7d10bcce8..a84cb8bbb 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd +++ b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd @@ -23,7 +23,7 @@ - + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp new file mode 100644 index 000000000..e69de29bb From 03ccfa1b6c4a1d93440f81e1c840529b637ce8c0 Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 8 Oct 2024 18:05:33 +0800 Subject: [PATCH 19/23] reformat code --- openfpga/src/annotation/write_unique_blocks.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp index 18d263714..0ea960ffc 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -211,8 +211,7 @@ int write_bin_atom_block(const std::vector>& instance_map, int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { ::capnp::MallocMessageBuilder builder; - auto unique_blocks = - builder.initRoot(); + auto unique_blocks = builder.initRoot(); int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); From f0a52bec18adf9c5a689765a858d3e5da48a1bf1 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 9 Oct 2024 14:15:39 +0800 Subject: [PATCH 20/23] auto generate capnp no compile error --- libs/libopenfpgacapnproto/CMakeLists.txt | 36 +---------------- .../gen/unique_blocks_uxsdcxx.capnp | 38 ++++++++++++++++++ libs/libopenfpgacapnproto/mmap_file.cpp | 39 ------------------- libs/libopenfpgacapnproto/mmap_file.h | 20 ---------- libs/libopenfpgacapnproto/serdes_utils.cpp | 23 ----------- libs/libopenfpgacapnproto/serdes_utils.h | 21 ---------- .../src/annotation/read_unique_blocks.cpp | 28 ++++++------- openfpga/src/annotation/read_unique_blocks.h | 5 +-- .../src/annotation/write_unique_blocks.cpp | 27 ++++++------- openfpga/src/annotation/write_unique_blocks.h | 4 +- 10 files changed, 71 insertions(+), 170 deletions(-) delete mode 100644 libs/libopenfpgacapnproto/mmap_file.cpp delete mode 100644 libs/libopenfpgacapnproto/mmap_file.h delete mode 100644 libs/libopenfpgacapnproto/serdes_utils.cpp delete mode 100644 libs/libopenfpgacapnproto/serdes_utils.h diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt index da04f7ecd..c81ab82f3 100644 --- a/libs/libopenfpgacapnproto/CMakeLists.txt +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -17,9 +17,6 @@ if(NOT MSCV) endif() # Create generated headers from capnp schema files -# -# Each schema used should appear here. - set(CAPNP_DEFS gen/unique_blocks_uxsdcxx.capnp ) @@ -30,42 +27,13 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS -find_program(WGET wget REQUIRED) -find_package(ZLIB REQUIRED) - -# Add Java schema -set(JAVA_SCHEMA ${CMAKE_CURRENT_BINARY_DIR}/schema/capnp/java.capnp) -add_custom_command( - OUTPUT ${JAVA_SCHEMA} - COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/schema/capnp/ - COMMAND ${WGET} - https://raw.githubusercontent.com/capnproto/capnproto-java/master/compiler/src/main/schema/capnp/java.capnp - -O ${JAVA_SCHEMA} -) - -add_custom_target( - get_java_capnp_schema_openfpga - DEPENDS ${JAVA_SCHEMA} -) - -set(CAPNPC_IMPORT_DIRS) -list(APPEND CAPNPC_IMPORT_DIRS ${CMAKE_CURRENT_BINARY_DIR}/schema) - - -install(FILES ${CAPNP_DEFS} DESTINATION ${CMAKE_INSTALL_DATADIR}/openfpga) - add_library(libopenfpgacapnproto STATIC ${CAPNP_SRCS} ${IC_SRCS} - mmap_file.h - mmap_file.cpp - serdes_utils.h - serdes_utils.cpp ) add_dependencies(libopenfpgacapnproto - get_java_capnp_schema_openfpga generate_unique_block_capnp ) @@ -77,7 +45,7 @@ target_include_directories(libopenfpgacapnproto PUBLIC ) target_link_libraries(libopenfpgacapnproto libopenfpgautil - CapnProto::capnp + libvtrcapnproto ) @@ -93,7 +61,7 @@ add_custom_target( unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h ${CMAKE_CURRENT_SOURCE_DIR}/gen - COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/../libopenfpgacapnproto/gen + COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/gen DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) \ No newline at end of file diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp index e69de29bb..9c370820f 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -0,0 +1,38 @@ +# This file is generated by uxsdcap 0.1.0. +# https://github.com/duck2/uxsdcxx +# Modify only if your build process doesn't involve regenerating this file. +# +# Cmdline: uxsdcxx/uxsdcap.py /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen +# Input file: /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd +# md5sum of input file: 6fd16e8f6b3530e875f67cea3044e719 + +@0xf133a161f333ac8a; +using Cxx = import "/capnp/c++.capnp"; +$Cxx.namespace("ucap"); + +enum Blocktype { + uxsdInvalid @0; + cbx @1; + cby @2; + sb @3; +} + +struct Blockinfo { + type @0 :Blocktype; + x @1 :UInt32; + y @2 :UInt32; +} + +struct Instanceinfo { + x @0 :UInt32; + y @1 :UInt32; +} + +struct Uniqueblockpacked { + blockinfo @0 :Blockinfo; + instances @1 :List(Instanceinfo); +} + +struct UniqueBlocks { + atominfos @0 :List(Uniqueblockpacked); +} diff --git a/libs/libopenfpgacapnproto/mmap_file.cpp b/libs/libopenfpgacapnproto/mmap_file.cpp deleted file mode 100644 index caa697ef7..000000000 --- a/libs/libopenfpgacapnproto/mmap_file.cpp +++ /dev/null @@ -1,39 +0,0 @@ -#include "mmap_file.h" - -#include -#include - -#include "vtr_error.h" -#include "vtr_util.h" -#ifndef _WIN32 -#include -#endif -#include - -#include "kj/filesystem.h" - -MmapFile::MmapFile(const std::string& file) : size_(0) { - try { - auto fs = kj::newDiskFilesystem(); - auto path = fs->getCurrentPath().evalNative(file); - - const auto& dir = fs->getRoot(); - auto stat = dir.lstat(path); - auto f = dir.openFile(path); - size_ = stat.size; - data_ = f->mmap(0, stat.size); - } catch (kj::Exception& e) { - throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); - } -} - -const kj::ArrayPtr MmapFile::getData() const { - if ((size_ % sizeof(::capnp::word)) != 0) { - throw vtr::VtrError( - vtr::string_fmt("size_ %d is not a multiple of capnp::word", size_), - __FILE__, __LINE__); - } - - return kj::arrayPtr(reinterpret_cast(data_.begin()), - size_ / sizeof(::capnp::word)); -} diff --git a/libs/libopenfpgacapnproto/mmap_file.h b/libs/libopenfpgacapnproto/mmap_file.h deleted file mode 100644 index 4b3d0ff25..000000000 --- a/libs/libopenfpgacapnproto/mmap_file.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef MMAP_FILE_H_ -#define MMAP_FILE_H_ - -#include - -#include "capnp/message.h" -#include "kj/array.h" - -// Platform independent mmap, useful for reading large capnp's. -class MmapFile { - public: - explicit MmapFile(const std::string& file); - const kj::ArrayPtr getData() const; - - private: - size_t size_; - kj::Array data_; -}; - -#endif /* MMAP_FILE_H_ */ diff --git a/libs/libopenfpgacapnproto/serdes_utils.cpp b/libs/libopenfpgacapnproto/serdes_utils.cpp deleted file mode 100644 index 88d84a455..000000000 --- a/libs/libopenfpgacapnproto/serdes_utils.cpp +++ /dev/null @@ -1,23 +0,0 @@ -#include "serdes_utils.h" - -#include -#include - -#include "kj/filesystem.h" -#include "vtr_error.h" - -void writeMessageToFile(const std::string& file, - ::capnp::MessageBuilder* builder) { - try { - auto fs = kj::newDiskFilesystem(); - auto path = fs->getCurrentPath().evalNative(file); - - const auto& dir = fs->getRoot(); - auto f = dir.openFile(path, kj::WriteMode::CREATE | kj::WriteMode::MODIFY); - f->truncate(0); - auto f_app = kj::newFileAppender(std::move(f)); - capnp::writeMessage(*f_app, *builder); - } catch (kj::Exception& e) { - throw vtr::VtrError(e.getDescription().cStr(), e.getFile(), e.getLine()); - } -} diff --git a/libs/libopenfpgacapnproto/serdes_utils.h b/libs/libopenfpgacapnproto/serdes_utils.h deleted file mode 100644 index 0c961d314..000000000 --- a/libs/libopenfpgacapnproto/serdes_utils.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef SERDES_UTILS_H_ -#define SERDES_UTILS_H_ - -#include -#include - -#include "capnp/serialize.h" - -// Platform indepedent way to file message to a file on disk. -void writeMessageToFile(const std::string& file, - ::capnp::MessageBuilder* builder); - -inline ::capnp::ReaderOptions default_large_capnp_opts() { - ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); - - /* Remove traversal limit */ - opts.traversalLimitInWords = std::numeric_limits::max(); - return opts; -} - -#endif /* SERDES_UTILS_H_ */ diff --git a/openfpga/src/annotation/read_unique_blocks.cpp b/openfpga/src/annotation/read_unique_blocks.cpp index 8e390279e..b8a0bef09 100644 --- a/openfpga/src/annotation/read_unique_blocks.cpp +++ b/openfpga/src/annotation/read_unique_blocks.cpp @@ -162,10 +162,10 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /*read the instances' coordinate of a unique block from a bin file*/ std::vector> read_bin_unique_instance_coords( - const uniqueblockcap::UniqueBlockPacked::Reader& unique_block) { + const ucap::Uniqueblockpacked::Reader& unique_block) { std::vector> instance_coords; - if (unique_block.hasInstanceList()) { - auto instance_list = unique_block.getInstanceList(); + if (unique_block.hasInstances()) { + auto instance_list = unique_block.getInstances(); for (auto instance : instance_list) { int instance_x = instance.getX(); int instance_y = instance.getY(); @@ -178,9 +178,8 @@ std::vector> read_bin_unique_instance_coords( /*read the unique block coordinate from a bin file */ vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::UniqueBlockPacked::Reader& unique_block, - uniqueblockcap::BlockType& type) { - auto block_info = unique_block.getBlockInfo(); + const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type) { + auto block_info = unique_block.getBlockinfo(); int block_x = block_info.getX(); int block_y = block_info.getY(); type = block_info.getType(); @@ -196,11 +195,11 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, device_rr_gsb.reserve_unique_modules(); MmapFile f(file_name); ::capnp::FlatArrayMessageReader reader(f.getData()); - auto root = reader.getRoot(); - if (root.hasAtomInfo()) { - auto block_list = root.getAtomInfo(); + auto root = reader.getRoot(); + if (root.hasAtominfos()) { + auto block_list = root.getAtominfos(); for (auto unique_block : block_list) { - uniqueblockcap::BlockType type; + ucap::Blocktype type; vtr::Point block_coordinate = read_bin_unique_block_coord( unique_block, type); /*get block coordinate and type*/ std::vector> instance_coords = @@ -208,15 +207,18 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, unique_block); /* get a list of instance coordinates*/ /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ - if (type == uniqueblockcap::BlockType::SB) { + if (type == ucap::Blocktype::SB) { device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); - } else if (type == uniqueblockcap::BlockType::CBY) { + } else if (type == ucap::Blocktype::CBY) { device_rr_gsb.preload_unique_cby_module(block_coordinate, instance_coords); - } else if (type == uniqueblockcap::BlockType::CBX) { + } else if (type == ucap::Blocktype::CBX) { device_rr_gsb.preload_unique_cbx_module(block_coordinate, instance_coords); + } else if (type == ucap::Blocktype::UXSD_INVALID) { + VTR_LOG_ERROR("Invalid block type!"); + return CMD_EXEC_FATAL_ERROR; } } } diff --git a/openfpga/src/annotation/read_unique_blocks.h b/openfpga/src/annotation/read_unique_blocks.h index 84f81502b..a65c54ac3 100644 --- a/openfpga/src/annotation/read_unique_blocks.h +++ b/openfpga/src/annotation/read_unique_blocks.h @@ -37,11 +37,10 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); std::vector> read_bin_unique_instance_coords( - const uniqueblockcap::UniqueBlockPacked::Reader& unique_block); + const ucap::Uniqueblockpacked::Reader& unique_block); vtr::Point read_bin_unique_block_coord( - const uniqueblockcap::UniqueBlockPacked::Reader& unique_block, - uniqueblockcap::BlockType& type); + const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type); int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks.cpp index 0ea960ffc..d4e9e1555 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks.cpp @@ -189,14 +189,14 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, * instances' info)into capnp builder */ int write_bin_atom_block(const std::vector>& instance_map, const vtr::Point& unique_block_coord, - const uniqueblockcap::BlockType type, - uniqueblockcap::UniqueBlockPacked::Builder& root) { - auto block_info = root.initBlockInfo(); + const ucap::Blocktype type, + ucap::Uniqueblockpacked::Builder& root) { + auto block_info = root.initBlockinfo(); block_info.setX(unique_block_coord.x()); block_info.setY(unique_block_coord.y()); block_info.setType(type); if (instance_map.size() > 0) { - auto instance_list = root.initInstanceList(instance_map.size()); + auto instance_list = root.initInstances(instance_map.size()); for (size_t instance_id = 0; instance_id < instance_map.size(); instance_id++) { auto instance = instance_list[instance_id]; @@ -211,11 +211,11 @@ int write_bin_atom_block(const std::vector>& instance_map, int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { ::capnp::MallocMessageBuilder builder; - auto unique_blocks = builder.initRoot(); + auto unique_blocks = builder.initRoot(); int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); - auto block_list = unique_blocks.initAtomInfo(num_unique_blocks); + auto block_list = unique_blocks.initAtominfos(num_unique_blocks); /*write switch blocks into bin file */ for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { @@ -223,9 +223,8 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, const std::vector> instance_map = device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); auto unique_block = block_list[id]; - int status_code = - write_bin_atom_block(instance_map, unique_block_coord, - uniqueblockcap::BlockType::SB, unique_block); + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::SB, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; @@ -241,9 +240,8 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); int block_id = id + device_rr_gsb.get_num_sb_unique_module(); auto unique_block = block_list[block_id]; - int status_code = - write_bin_atom_block(instance_map, unique_block_coord, - uniqueblockcap::BlockType::CBX, unique_block); + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::CBX, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; @@ -260,9 +258,8 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, int block_id = id + device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX); auto unique_block = block_list[block_id]; - int status_code = - write_bin_atom_block(instance_map, unique_block_coord, - uniqueblockcap::BlockType::CBY, unique_block); + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::CBY, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/annotation/write_unique_blocks.h b/openfpga/src/annotation/write_unique_blocks.h index 6b56c67ff..d6f69e021 100644 --- a/openfpga/src/annotation/write_unique_blocks.h +++ b/openfpga/src/annotation/write_unique_blocks.h @@ -37,7 +37,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); int write_bin_atom_block(const std::vector>& instance_map, const vtr::Point& unique_block_coord, - const uniqueblockcap::BlockType type, - uniqueblockcap::UniqueBlockPacked::Builder& root); + const ucap::Blocktype type, + ucap::Uniqueblockpacked::Builder& root); } // namespace openfpga #endif From 4d8fae94a431a774255eebb3a4d83b5805774d7f Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 9 Oct 2024 14:32:58 +0800 Subject: [PATCH 21/23] seperate xml parser and bin parser --- .../src/annotation/read_unique_blocks_bin.cpp | 104 +++++++++++++++ .../src/annotation/read_unique_blocks_bin.h | 36 ++++++ ..._blocks.cpp => read_unique_blocks_xml.cpp} | 71 +--------- ...ique_blocks.h => read_unique_blocks_xml.h} | 13 +- .../annotation/write_unique_blocks_bin.cpp | 121 ++++++++++++++++++ .../src/annotation/write_unique_blocks_bin.h | 34 +++++ ...blocks.cpp => write_unique_blocks_xml.cpp} | 91 +------------ ...que_blocks.h => write_unique_blocks_xml.h} | 10 +- .../src/base/openfpga_build_fabric_template.h | 6 +- 9 files changed, 305 insertions(+), 181 deletions(-) create mode 100644 openfpga/src/annotation/read_unique_blocks_bin.cpp create mode 100644 openfpga/src/annotation/read_unique_blocks_bin.h rename openfpga/src/annotation/{read_unique_blocks.cpp => read_unique_blocks_xml.cpp} (69%) rename openfpga/src/annotation/{read_unique_blocks.h => read_unique_blocks_xml.h} (73%) create mode 100644 openfpga/src/annotation/write_unique_blocks_bin.cpp create mode 100644 openfpga/src/annotation/write_unique_blocks_bin.h rename openfpga/src/annotation/{write_unique_blocks.cpp => write_unique_blocks_xml.cpp} (62%) rename openfpga/src/annotation/{write_unique_blocks.h => write_unique_blocks_xml.h} (71%) diff --git a/openfpga/src/annotation/read_unique_blocks_bin.cpp b/openfpga/src/annotation/read_unique_blocks_bin.cpp new file mode 100644 index 000000000..b11087420 --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_bin.cpp @@ -0,0 +1,104 @@ +#include +#include +#include + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "mmap_file.h" +#include "openfpga_digest.h" +#include "read_unique_blocks_bin.h" +#include "read_unique_blocks_xml.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads a bin file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { + +/*read the instances' coordinate of a unique block from a bin file*/ +std::vector> read_bin_unique_instance_coords( + const ucap::Uniqueblockpacked::Reader& unique_block) { + std::vector> instance_coords; + if (unique_block.hasInstances()) { + auto instance_list = unique_block.getInstances(); + for (auto instance : instance_list) { + int instance_x = instance.getX(); + int instance_y = instance.getY(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + return instance_coords; +} + +/*read the unique block coordinate from a bin file */ +vtr::Point read_bin_unique_block_coord( + const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type) { + auto block_info = unique_block.getBlockinfo(); + int block_x = block_info.getX(); + int block_y = block_info.getY(); + type = block_info.getType(); + vtr::Point block_coordinate(block_x, block_y); + return block_coordinate; +} + +/*top-level function to read unique blocks from bin file*/ +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + /* clear unique modules & reserve memory to relavant vectors */ + device_rr_gsb.clear_unique_modules(); + device_rr_gsb.reserve_unique_modules(); + MmapFile f(file_name); + ::capnp::FlatArrayMessageReader reader(f.getData()); + auto root = reader.getRoot(); + if (root.hasAtominfos()) { + auto block_list = root.getAtominfos(); + for (auto unique_block : block_list) { + ucap::Blocktype type; + vtr::Point block_coordinate = read_bin_unique_block_coord( + unique_block, type); /*get block coordinate and type*/ + std::vector> instance_coords = + read_bin_unique_instance_coords( + unique_block); /* get a list of instance coordinates*/ + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ + if (type == ucap::Blocktype::SB) { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == ucap::Blocktype::CBY) { + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); + } else if (type == ucap::Blocktype::CBX) { + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); + } else if (type == ucap::Blocktype::UXSD_INVALID) { + VTR_LOG_ERROR("Invalid block type!"); + return CMD_EXEC_FATAL_ERROR; + } + } + } + device_rr_gsb.build_gsb_unique_module(); + if (verbose_output) { + report_unique_module_status_read(device_rr_gsb, true); + } + return CMD_EXEC_SUCCESS; +} +} // namespace openfpga diff --git a/openfpga/src/annotation/read_unique_blocks_bin.h b/openfpga/src/annotation/read_unique_blocks_bin.h new file mode 100644 index 000000000..2e7281b69 --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_bin.h @@ -0,0 +1,36 @@ +#ifndef READ_XML_UNIQUE_BLOCKS_BIN_H +#define READ_XML_UNIQUE_BLOCKS_BIN_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" +#include "unique_blocks_uxsdcxx.capnp.h" +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads a bin file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { +std::vector> read_bin_unique_instance_coords( + const ucap::Uniqueblockpacked::Reader& unique_block); + +vtr::Point read_bin_unique_block_coord( + const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type); + +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output); +} // namespace openfpga + +#endif diff --git a/openfpga/src/annotation/read_unique_blocks.cpp b/openfpga/src/annotation/read_unique_blocks_xml.cpp similarity index 69% rename from openfpga/src/annotation/read_unique_blocks.cpp rename to openfpga/src/annotation/read_unique_blocks_xml.cpp index b8a0bef09..bd462b147 100644 --- a/openfpga/src/annotation/read_unique_blocks.cpp +++ b/openfpga/src/annotation/read_unique_blocks_xml.cpp @@ -18,7 +18,7 @@ #include "device_rr_gsb_utils.h" #include "mmap_file.h" #include "openfpga_digest.h" -#include "read_unique_blocks.h" +#include "read_unique_blocks_xml.h" #include "read_xml_util.h" #include "rr_gsb.h" #include "unique_blocks_uxsdcxx.capnp.h" @@ -159,73 +159,4 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, archfpga_throw(file_name, e.line(), "%s", e.what()); } } - -/*read the instances' coordinate of a unique block from a bin file*/ -std::vector> read_bin_unique_instance_coords( - const ucap::Uniqueblockpacked::Reader& unique_block) { - std::vector> instance_coords; - if (unique_block.hasInstances()) { - auto instance_list = unique_block.getInstances(); - for (auto instance : instance_list) { - int instance_x = instance.getX(); - int instance_y = instance.getY(); - vtr::Point instance_coordinate(instance_x, instance_y); - instance_coords.push_back(instance_coordinate); - } - } - return instance_coords; -} - -/*read the unique block coordinate from a bin file */ -vtr::Point read_bin_unique_block_coord( - const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type) { - auto block_info = unique_block.getBlockinfo(); - int block_x = block_info.getX(); - int block_y = block_info.getY(); - type = block_info.getType(); - vtr::Point block_coordinate(block_x, block_y); - return block_coordinate; -} - -/*top-level function to read unique blocks from bin file*/ -int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, - bool verbose_output) { - /* clear unique modules & reserve memory to relavant vectors */ - device_rr_gsb.clear_unique_modules(); - device_rr_gsb.reserve_unique_modules(); - MmapFile f(file_name); - ::capnp::FlatArrayMessageReader reader(f.getData()); - auto root = reader.getRoot(); - if (root.hasAtominfos()) { - auto block_list = root.getAtominfos(); - for (auto unique_block : block_list) { - ucap::Blocktype type; - vtr::Point block_coordinate = read_bin_unique_block_coord( - unique_block, type); /*get block coordinate and type*/ - std::vector> instance_coords = - read_bin_unique_instance_coords( - unique_block); /* get a list of instance coordinates*/ - /* get block coordinate and instance coordinate, try to setup - * device_rr_gsb */ - if (type == ucap::Blocktype::SB) { - device_rr_gsb.preload_unique_sb_module(block_coordinate, - instance_coords); - } else if (type == ucap::Blocktype::CBY) { - device_rr_gsb.preload_unique_cby_module(block_coordinate, - instance_coords); - } else if (type == ucap::Blocktype::CBX) { - device_rr_gsb.preload_unique_cbx_module(block_coordinate, - instance_coords); - } else if (type == ucap::Blocktype::UXSD_INVALID) { - VTR_LOG_ERROR("Invalid block type!"); - return CMD_EXEC_FATAL_ERROR; - } - } - } - device_rr_gsb.build_gsb_unique_module(); - if (verbose_output) { - report_unique_module_status_read(device_rr_gsb, true); - } - return CMD_EXEC_SUCCESS; -} } // namespace openfpga diff --git a/openfpga/src/annotation/read_unique_blocks.h b/openfpga/src/annotation/read_unique_blocks_xml.h similarity index 73% rename from openfpga/src/annotation/read_unique_blocks.h rename to openfpga/src/annotation/read_unique_blocks_xml.h index a65c54ac3..241bc07e2 100644 --- a/openfpga/src/annotation/read_unique_blocks.h +++ b/openfpga/src/annotation/read_unique_blocks_xml.h @@ -1,5 +1,5 @@ -#ifndef READ_XML_UNIQUE_BLOCKS_H -#define READ_XML_UNIQUE_BLOCKS_H +#ifndef READ_XML_UNIQUE_BLOCKS_XML_H +#define READ_XML_UNIQUE_BLOCKS_XML_H #include @@ -35,15 +35,6 @@ void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); - -std::vector> read_bin_unique_instance_coords( - const ucap::Uniqueblockpacked::Reader& unique_block); - -vtr::Point read_bin_unique_block_coord( - const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type); - -int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, - bool verbose_output); } // namespace openfpga #endif diff --git a/openfpga/src/annotation/write_unique_blocks_bin.cpp b/openfpga/src/annotation/write_unique_blocks_bin.cpp new file mode 100644 index 000000000..0b53e530b --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_bin.cpp @@ -0,0 +1,121 @@ + +#include + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" +#include "serdes_utils.h" +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_unique_blocks_bin.h" +#include "write_unique_blocks_xml.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a bin file + *******************************************************************/ +namespace openfpga { +/* write each unique block (including a single unique block info and its mirror + * instances' info)into capnp builder */ +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const ucap::Blocktype type, + ucap::Uniqueblockpacked::Builder& root) { + auto block_info = root.initBlockinfo(); + block_info.setX(unique_block_coord.x()); + block_info.setY(unique_block_coord.y()); + block_info.setType(type); + if (instance_map.size() > 0) { + auto instance_list = root.initInstances(instance_map.size()); + for (size_t instance_id = 0; instance_id < instance_map.size(); + instance_id++) { + auto instance = instance_list[instance_id]; + instance.setX(instance_map[instance_id].x()); + instance.setY(instance_map[instance_id].y()); + } + } + return openfpga::CMD_EXEC_SUCCESS; +} + +/* Top-level function to write bin file of unique blocks */ +int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output) { + ::capnp::MallocMessageBuilder builder; + auto unique_blocks = builder.initRoot(); + int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX) + + device_rr_gsb.get_num_cb_unique_module(CHANY); + auto block_list = unique_blocks.initAtominfos(num_unique_blocks); + + /*write switch blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + auto unique_block = block_list[id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::SB, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + /*write cbx blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cbx_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module(); + auto unique_block = block_list[block_id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::CBX, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + /*write cby blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cby_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX); + auto unique_block = block_list[block_id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Blocktype::CBY, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + writeMessageToFile(fname, &builder); + if (verbose_output) { + report_unique_module_status_write(device_rr_gsb, true); + } + return openfpga::CMD_EXEC_SUCCESS; +} + +} // namespace openfpga diff --git a/openfpga/src/annotation/write_unique_blocks_bin.h b/openfpga/src/annotation/write_unique_blocks_bin.h new file mode 100644 index 000000000..da4b39944 --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_bin.h @@ -0,0 +1,34 @@ +#ifndef WRITE_XML_UNIQUE_BLOCKS_BIN_H +#define WRITE_XML_UNIQUE_BLOCKS_BIN_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a bin file + *******************************************************************/ + +namespace openfpga { +int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output); +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const ucap::Blocktype type, + ucap::Uniqueblockpacked::Builder& root); +} // namespace openfpga +#endif diff --git a/openfpga/src/annotation/write_unique_blocks.cpp b/openfpga/src/annotation/write_unique_blocks_xml.cpp similarity index 62% rename from openfpga/src/annotation/write_unique_blocks.cpp rename to openfpga/src/annotation/write_unique_blocks_xml.cpp index d4e9e1555..e9950f015 100644 --- a/openfpga/src/annotation/write_unique_blocks.cpp +++ b/openfpga/src/annotation/write_unique_blocks_xml.cpp @@ -19,7 +19,7 @@ #include "read_xml_util.h" #include "rr_gsb.h" #include "unique_blocks_uxsdcxx.capnp.h" -#include "write_unique_blocks.h" +#include "write_unique_blocks_xml.h" #include "write_xml_utils.h" /******************************************************************** @@ -184,93 +184,4 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, return CMD_EXEC_SUCCESS; } - -/* write each unique block (including a single unique block info and its mirror - * instances' info)into capnp builder */ -int write_bin_atom_block(const std::vector>& instance_map, - const vtr::Point& unique_block_coord, - const ucap::Blocktype type, - ucap::Uniqueblockpacked::Builder& root) { - auto block_info = root.initBlockinfo(); - block_info.setX(unique_block_coord.x()); - block_info.setY(unique_block_coord.y()); - block_info.setType(type); - if (instance_map.size() > 0) { - auto instance_list = root.initInstances(instance_map.size()); - for (size_t instance_id = 0; instance_id < instance_map.size(); - instance_id++) { - auto instance = instance_list[instance_id]; - instance.setX(instance_map[instance_id].x()); - instance.setY(instance_map[instance_id].y()); - } - } - return openfpga::CMD_EXEC_SUCCESS; -} - -/* Top-level function to write bin file of unique blocks */ -int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, - bool verbose_output) { - ::capnp::MallocMessageBuilder builder; - auto unique_blocks = builder.initRoot(); - int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + - device_rr_gsb.get_num_cb_unique_module(CHANX) + - device_rr_gsb.get_num_cb_unique_module(CHANY); - auto block_list = unique_blocks.initAtominfos(num_unique_blocks); - - /*write switch blocks into bin file */ - for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { - const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); - const std::vector> instance_map = - device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); - auto unique_block = block_list[id]; - int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::SB, unique_block); - if (status_code != 0) { - VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); - return CMD_EXEC_FATAL_ERROR; - } - } - - /*write cbx blocks into bin file */ - for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); - ++id) { - const auto unique_block_coord = - device_rr_gsb.get_cbx_unique_block_coord(id); - const std::vector> instance_map = - device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); - int block_id = id + device_rr_gsb.get_num_sb_unique_module(); - auto unique_block = block_list[block_id]; - int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::CBX, unique_block); - if (status_code != 0) { - VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); - return CMD_EXEC_FATAL_ERROR; - } - } - - /*write cby blocks into bin file */ - for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); - ++id) { - const auto unique_block_coord = - device_rr_gsb.get_cby_unique_block_coord(id); - const std::vector> instance_map = - device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); - int block_id = id + device_rr_gsb.get_num_sb_unique_module() + - device_rr_gsb.get_num_cb_unique_module(CHANX); - auto unique_block = block_list[block_id]; - int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::CBY, unique_block); - if (status_code != 0) { - VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); - return CMD_EXEC_FATAL_ERROR; - } - } - - writeMessageToFile(fname, &builder); - if (verbose_output) { - report_unique_module_status_write(device_rr_gsb, true); - } - return openfpga::CMD_EXEC_SUCCESS; -} - } // namespace openfpga diff --git a/openfpga/src/annotation/write_unique_blocks.h b/openfpga/src/annotation/write_unique_blocks_xml.h similarity index 71% rename from openfpga/src/annotation/write_unique_blocks.h rename to openfpga/src/annotation/write_unique_blocks_xml.h index d6f69e021..0dafa5f47 100644 --- a/openfpga/src/annotation/write_unique_blocks.h +++ b/openfpga/src/annotation/write_unique_blocks_xml.h @@ -1,5 +1,5 @@ -#ifndef WRITE_XML_UNIQUE_BLOCKS_H -#define WRITE_XML_UNIQUE_BLOCKS_H +#ifndef WRITE_XML_UNIQUE_BLOCKS_XML_H +#define WRITE_XML_UNIQUE_BLOCKS_XML_H #include @@ -33,11 +33,5 @@ void report_unique_module_status_write( bool verbose_output); /*report status of written info*/ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); -int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, - bool verbose_output); -int write_bin_atom_block(const std::vector>& instance_map, - const vtr::Point& unique_block_coord, - const ucap::Blocktype type, - ucap::Uniqueblockpacked::Builder& root); } // namespace openfpga #endif diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 985bec349..1c1d23172 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -16,7 +16,8 @@ #include "fabric_key_writer.h" #include "globals.h" #include "openfpga_naming.h" -#include "read_unique_blocks.h" +#include "read_unique_blocks_bin.h" +#include "read_unique_blocks_xml.h" #include "read_xml_fabric_key.h" #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" @@ -25,7 +26,8 @@ #include "report_reference.h" #include "vtr_log.h" #include "vtr_time.h" -#include "write_unique_blocks.h" +#include "write_unique_blocks_bin.h" +#include "write_unique_blocks_xml.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" From 88e12a0afad9571c940188b8fb5c15c1fe71dafe Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 9 Oct 2024 17:21:49 +0800 Subject: [PATCH 22/23] modified test cases & xsd file --- libs/libopenfpgacapnproto/gen/README.gen.md | 2 +- .../gen/unique_blocks.xsd | 36 ++++---- .../gen/unique_blocks_uxsdcxx.capnp | 24 +++-- .../src/annotation/read_unique_blocks_bin.cpp | 25 +++--- .../src/annotation/read_unique_blocks_bin.h | 4 +- .../annotation/write_unique_blocks_bin.cpp | 18 ++-- .../src/annotation/write_unique_blocks_bin.h | 3 +- ...e_blocks_full_flow_example_script.openfpga | 79 ----------------- ...e_xml_uniqueblocks_example_script.openfpga | 82 ------------------ ...read_unique_blocks_example_script.openfpga | 52 ----------- ...e_blocks_full_flow_example_script.openfpga | 4 +- ...e_blocks_full_flow_example_script.openfpga | 8 +- ...e_blocks_full_flow_example_script.openfpga | 80 ----------------- ...rite_unique_blocks_example_script.openfpga | 49 ----------- ...e_blocks_full_flow_example_script.openfpga | 4 +- .../config/task.conf | 34 +++++--- .../read_bin_write_xml/config/tile_config.xml | 1 + .../read_bin_write_xml/read_unique_block.bin | Bin 0 -> 1080 bytes .../read_unique_blocks/read_unique_block.xml | 22 ----- .../read_unique_blocks_bin/config/task.conf | 5 +- .../config/task.conf | 3 +- .../read_write_unique_blocks/config/task.conf | 5 +- .../config/task.conf | 7 +- .../config/task.conf | 4 +- .../write_unique_blocks/config/task.conf | 35 -------- .../config/task.conf | 2 + 26 files changed, 99 insertions(+), 489 deletions(-) delete mode 100644 openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga delete mode 100644 openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga delete mode 100644 openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga delete mode 100644 openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga delete mode 100644 openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga rename openfpga_flow/tasks/basic_tests/preload_unique_blocks/{read_unique_blocks => read_bin_write_xml}/config/task.conf (51%) create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin delete mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml delete mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf diff --git a/libs/libopenfpgacapnproto/gen/README.gen.md b/libs/libopenfpgacapnproto/gen/README.gen.md index 8c08d1a30..6e66ee7e5 100644 --- a/libs/libopenfpgacapnproto/gen/README.gen.md +++ b/libs/libopenfpgacapnproto/gen/README.gen.md @@ -1,4 +1,4 @@ `unique_blocks_uxsdcxx.capnp` is generated via uxsdcxx and is checked in to -avoid requiring python3 and the uxsdcxx depedencies to build VPR. +avoid requiring python3 and the uxsdcxx depedencies to build Openfpga. diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd index a84cb8bbb..a68587320 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd +++ b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd @@ -2,7 +2,7 @@ - + @@ -10,33 +10,27 @@ - - - - - - - - - - + + + - - - - - - - + + + + + + + + + - + - - + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp index 9c370820f..46daa20d4 100644 --- a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -4,35 +4,31 @@ # # Cmdline: uxsdcxx/uxsdcap.py /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen # Input file: /home/jrlin/add_feature/bin_format/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd -# md5sum of input file: 6fd16e8f6b3530e875f67cea3044e719 +# md5sum of input file: 1db9d740309076fa51f61413bae1e072 -@0xf133a161f333ac8a; +@0xc5f2ef95c322aac3; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); -enum Blocktype { +enum Type { uxsdInvalid @0; cbx @1; cby @2; sb @3; } -struct Blockinfo { - type @0 :Blocktype; - x @1 :UInt32; - y @2 :UInt32; -} - -struct Instanceinfo { +struct Instance { x @0 :UInt32; y @1 :UInt32; } -struct Uniqueblockpacked { - blockinfo @0 :Blockinfo; - instances @1 :List(Instanceinfo); +struct Block { + type @0 :Type; + x @1 :UInt32; + y @2 :UInt32; + instances @3 :List(Instance); } struct UniqueBlocks { - atominfos @0 :List(Uniqueblockpacked); + blocks @0 :List(Block); } diff --git a/openfpga/src/annotation/read_unique_blocks_bin.cpp b/openfpga/src/annotation/read_unique_blocks_bin.cpp index b11087420..1d739403e 100644 --- a/openfpga/src/annotation/read_unique_blocks_bin.cpp +++ b/openfpga/src/annotation/read_unique_blocks_bin.cpp @@ -35,7 +35,7 @@ namespace openfpga { /*read the instances' coordinate of a unique block from a bin file*/ std::vector> read_bin_unique_instance_coords( - const ucap::Uniqueblockpacked::Reader& unique_block) { + const ucap::Block::Reader& unique_block) { std::vector> instance_coords; if (unique_block.hasInstances()) { auto instance_list = unique_block.getInstances(); @@ -51,11 +51,10 @@ std::vector> read_bin_unique_instance_coords( /*read the unique block coordinate from a bin file */ vtr::Point read_bin_unique_block_coord( - const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type) { - auto block_info = unique_block.getBlockinfo(); - int block_x = block_info.getX(); - int block_y = block_info.getY(); - type = block_info.getType(); + const ucap::Block::Reader& unique_block, ucap::Type& type) { + int block_x = unique_block.getX(); + int block_y = unique_block.getY(); + type = unique_block.getType(); vtr::Point block_coordinate(block_x, block_y); return block_coordinate; } @@ -69,10 +68,10 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, MmapFile f(file_name); ::capnp::FlatArrayMessageReader reader(f.getData()); auto root = reader.getRoot(); - if (root.hasAtominfos()) { - auto block_list = root.getAtominfos(); + if (root.hasBlocks()) { + auto block_list = root.getBlocks(); for (auto unique_block : block_list) { - ucap::Blocktype type; + ucap::Type type; vtr::Point block_coordinate = read_bin_unique_block_coord( unique_block, type); /*get block coordinate and type*/ std::vector> instance_coords = @@ -80,16 +79,16 @@ int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, unique_block); /* get a list of instance coordinates*/ /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ - if (type == ucap::Blocktype::SB) { + if (type == ucap::Type::SB) { device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); - } else if (type == ucap::Blocktype::CBY) { + } else if (type == ucap::Type::CBY) { device_rr_gsb.preload_unique_cby_module(block_coordinate, instance_coords); - } else if (type == ucap::Blocktype::CBX) { + } else if (type == ucap::Type::CBX) { device_rr_gsb.preload_unique_cbx_module(block_coordinate, instance_coords); - } else if (type == ucap::Blocktype::UXSD_INVALID) { + } else if (type == ucap::Type::UXSD_INVALID) { VTR_LOG_ERROR("Invalid block type!"); return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/annotation/read_unique_blocks_bin.h b/openfpga/src/annotation/read_unique_blocks_bin.h index 2e7281b69..54da11a3a 100644 --- a/openfpga/src/annotation/read_unique_blocks_bin.h +++ b/openfpga/src/annotation/read_unique_blocks_bin.h @@ -24,10 +24,10 @@ *******************************************************************/ namespace openfpga { std::vector> read_bin_unique_instance_coords( - const ucap::Uniqueblockpacked::Reader& unique_block); + const ucap::Block::Reader& unique_block); vtr::Point read_bin_unique_block_coord( - const ucap::Uniqueblockpacked::Reader& unique_block, ucap::Blocktype& type); + const ucap::Block::Reader& unique_block, ucap::Type& type); int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); diff --git a/openfpga/src/annotation/write_unique_blocks_bin.cpp b/openfpga/src/annotation/write_unique_blocks_bin.cpp index 0b53e530b..13dc53cec 100644 --- a/openfpga/src/annotation/write_unique_blocks_bin.cpp +++ b/openfpga/src/annotation/write_unique_blocks_bin.cpp @@ -34,12 +34,10 @@ namespace openfpga { * instances' info)into capnp builder */ int write_bin_atom_block(const std::vector>& instance_map, const vtr::Point& unique_block_coord, - const ucap::Blocktype type, - ucap::Uniqueblockpacked::Builder& root) { - auto block_info = root.initBlockinfo(); - block_info.setX(unique_block_coord.x()); - block_info.setY(unique_block_coord.y()); - block_info.setType(type); + const ucap::Type type, ucap::Block::Builder& root) { + root.setX(unique_block_coord.x()); + root.setY(unique_block_coord.y()); + root.setType(type); if (instance_map.size() > 0) { auto instance_list = root.initInstances(instance_map.size()); for (size_t instance_id = 0; instance_id < instance_map.size(); @@ -60,7 +58,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + device_rr_gsb.get_num_cb_unique_module(CHANX) + device_rr_gsb.get_num_cb_unique_module(CHANY); - auto block_list = unique_blocks.initAtominfos(num_unique_blocks); + auto block_list = unique_blocks.initBlocks(num_unique_blocks); /*write switch blocks into bin file */ for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { @@ -69,7 +67,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); auto unique_block = block_list[id]; int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::SB, unique_block); + ucap::Type::SB, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; @@ -86,7 +84,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, int block_id = id + device_rr_gsb.get_num_sb_unique_module(); auto unique_block = block_list[block_id]; int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::CBX, unique_block); + ucap::Type::CBX, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; @@ -104,7 +102,7 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, device_rr_gsb.get_num_cb_unique_module(CHANX); auto unique_block = block_list[block_id]; int status_code = write_bin_atom_block(instance_map, unique_block_coord, - ucap::Blocktype::CBY, unique_block); + ucap::Type::CBY, unique_block); if (status_code != 0) { VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/annotation/write_unique_blocks_bin.h b/openfpga/src/annotation/write_unique_blocks_bin.h index da4b39944..e49fc095e 100644 --- a/openfpga/src/annotation/write_unique_blocks_bin.h +++ b/openfpga/src/annotation/write_unique_blocks_bin.h @@ -28,7 +28,6 @@ int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); int write_bin_atom_block(const std::vector>& instance_map, const vtr::Point& unique_block_coord, - const ucap::Blocktype type, - ucap::Uniqueblockpacked::Builder& root); + const ucap::Type type, ucap::Block::Builder& root); } // namespace openfpga #endif diff --git a/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga deleted file mode 100644 index 62db921b2..000000000 --- a/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga +++ /dev/null @@ -1,79 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Optionally pb pin fixup -${OPENFPGA_PB_PIN_FIXUP_COMMAND} - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup - -# preload unique blocks from the provided xml file -read_unique_blocks --file ${READ_UNIQUE_BLOCKS_BIN} --verbose --type bin - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.bit --format plain_text - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} - -# Write the SDC files for PnR backend -# - Turn on every options here -# FIXME: Not supported yet. -#write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga deleted file mode 100644 index 843c36ae7..000000000 --- a/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga +++ /dev/null @@ -1,82 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Optionally pb pin fixup -${OPENFPGA_PB_PIN_FIXUP_COMMAND} - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup - -# preload unique blocks from the provided xml file -read_unique_blocks --file ${READ_UNIQUE_BLOCKS_BIN} --verbose --type bin - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose - -#write unique blocks xml file -write_unique_blocks --file ./write_unique_block.xml --verbose --type xml - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.bit --format plain_text - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} - -# Write the SDC files for PnR backend -# - Turn on every options here -# FIXME: Not supported yet. -#write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga deleted file mode 100644 index a311e9870..000000000 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga +++ /dev/null @@ -1,52 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# preload unique blocks from the provided xml file -read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric #--verbose - -#write unique blocks xml file -write_unique_blocks --file ./write_unique_block.xml --verbose --type xml - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Write the fabric I/O attributes to a file -# This is used by pin constraint files -write_fabric_io_info --file ./fabric_io_location.xml --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga index 649999219..9114dac0a 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga @@ -21,8 +21,8 @@ ${OPENFPGA_PB_PIN_FIXUP_COMMAND} # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup -# preload unique blocks from the provided xml file -read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml +# preload unique blocks from the provided file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE} # Build the module graph # - Enabled compression on routing architecture modules diff --git a/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga index 715478707..5718bd4e8 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga @@ -21,16 +21,16 @@ ${OPENFPGA_PB_PIN_FIXUP_COMMAND} # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup -# preload unique blocks from the provided xml file -read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml +# preload unique blocks from the provided file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE_READ} # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose -#write unique blocks to a xml format file -write_unique_blocks --file ./write_unique_block.xml --verbose --type xml +#write unique blocks to a format file +write_unique_blocks --file ./${WRITE_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE_WRITE} # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga deleted file mode 100644 index 1c07f8b7c..000000000 --- a/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga +++ /dev/null @@ -1,80 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Optionally pb pin fixup -${OPENFPGA_PB_PIN_FIXUP_COMMAND} - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup - - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose - -#write unique blocks xml file -write_unique_blocks --file ./write_unique_block.bin --verbose --type bin - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.bit --format plain_text - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} - -# Write the SDC files for PnR backend -# - Turn on every options here -# FIXME: Not supported yet. -#write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga deleted file mode 100644 index 8df291ccc..000000000 --- a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga +++ /dev/null @@ -1,49 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing #--verbose - -#write unique blocks xml file -write_unique_blocks --file ./write_unique_block.xml --verbose --type xml - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Write the fabric I/O attributes to a file -# This is used by pin constraint files -write_fabric_io_info --file ./fabric_io_location.xml --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga index 5de0100c1..f5fcbb960 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga @@ -27,8 +27,8 @@ lut_truth_table_fixup # - Enable pin duplication on grid modules build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose -#write unique blocks xml file -write_unique_blocks --file ./write_unique_block.xml --verbose --type xml +#write unique blocks file +write_unique_blocks --file ./${WRITE_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE} # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf similarity index 51% rename from openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf rename to openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf index 77ec87990..ca93b9ec3 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf @@ -9,27 +9,37 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file_read=bin +openfpga_unique_block_file_write=xml +write_unique_blocks=write_unique_block.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v [SYNTHESIS_PARAM] -bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench_read_verilog_options_common = -nolatches +bench0_top = or2 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] - +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin new file mode 100644 index 0000000000000000000000000000000000000000..40563887393d714a5d67c4bded0bb671dbc5252b GIT binary patch literal 1080 zcmZ{fp;7}u5JWc#0)dZ76^D<(M82$uQj9BkE8z-z73v-ehJfm9XixY z{T4<4J*fNDAMx4uIr?AW`(TqFAb%CU3~z_N4wK&veHSKw9QqU{zY1!p)9!ViuV>#y z#@yK)>)ITab9DxvIdW#FqRHZu@eB*^tr - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf index 41a49a326..53e0da4dd 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_unique_blocks_full_flow_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_bin =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file=bin openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf index 5ab911a8b..bd72c7d3e 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf @@ -19,7 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_unique_block_file=xml openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf index f7a3fab83..4246bdcdc 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf @@ -19,7 +19,10 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_unique_block_file_read=xml +openfpga_unique_block_file_write=xml +write_unique_blocks=write_unique_block.xml openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf index f942d71fc..3a30ebb5f 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf @@ -16,10 +16,13 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_bin_write_xml_uniqueblocks_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -read_unique_blocks_bin =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file_read=bin +openfpga_unique_block_file_write=bin +write_unique_blocks=write_unique_block.bin openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf index bc6bcd521..82ad03f4b 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_bin_unique_blocks_full_flow_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +write_unique_blocks=write_unique_block.bin +openfpga_unique_block_file=bin openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf deleted file mode 100644 index 2f8171066..000000000 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf +++ /dev/null @@ -1,35 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] - diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf index 88dacdc64..f82062160 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf @@ -19,6 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +write_unique_blocks=write_unique_blocks.xml +openfpga_unique_block_file=xml openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 From fc5c0f6965f6304354cc30452bee6578119db97f Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 9 Oct 2024 17:41:01 +0800 Subject: [PATCH 23/23] modified testcases --- .../src/annotation/read_unique_blocks_xml.cpp | 3 --- .../regression_test_scripts/basic_reg_test.sh | 3 +-- .../read_bin_write_xml/read_unique_block.bin | Bin 1080 -> 960 bytes .../read_unique_block.bin | Bin 1080 -> 960 bytes .../read_unique_block.bin | Bin 1080 -> 960 bytes 5 files changed, 1 insertion(+), 5 deletions(-) diff --git a/openfpga/src/annotation/read_unique_blocks_xml.cpp b/openfpga/src/annotation/read_unique_blocks_xml.cpp index bd462b147..201c253c2 100644 --- a/openfpga/src/annotation/read_unique_blocks_xml.cpp +++ b/openfpga/src/annotation/read_unique_blocks_xml.cpp @@ -1,6 +1,3 @@ -#include -#include -#include #include /* Headers from pugi XML library */ diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 0c7de95d6..4e1226b0c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -19,14 +19,13 @@ run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ echo -e "Testing preloading unique blocks" -run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ -run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@ run-task basic_tests/preload_unique_blocks/read_write_unique_blocks $@ run-task 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