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Hot fix

This commit is contained in:
Baudouin Chauviere 2019-10-01 16:40:16 -06:00
parent 633a12ee08
commit 7c3ab38410
2 changed files with 41 additions and 29 deletions
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17
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
View File

@ -60,3 +60,20 @@ vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_x2p_compact_routing_hierarchy= vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test= end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
fix_route_chan_width=300
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_x2p_compact_routing_hierarchy=
vpr_fpga_verilog_explicit_mapping=
end_flow_with_test=

53
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -1110,27 +1110,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
switch (rr_chan.get_node(itrack)->direction) { switch (rr_chan.get_node(itrack)->direction) {
case INC_DIRECTION: case INC_DIRECTION:
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ".in%d (",itrack); fprintf(fp, ".in%d (",itrack);
} }
fprintf(fp, "%s", fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, OUT_PORT)); x, y, itrack, OUT_PORT));
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ",\n"); fprintf(fp, ",\n");
break; break;
case DEC_DIRECTION: case DEC_DIRECTION:
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ".out%d (",itrack); fprintf(fp, ".out%d (",itrack);
} }
fprintf(fp, "%s", fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, IN_PORT)); x, y, itrack, IN_PORT));
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ",\n"); fprintf(fp, ",\n");
break; break;
default: default:
@ -1150,27 +1150,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
switch (rr_chan.get_node(itrack)->direction) { switch (rr_chan.get_node(itrack)->direction) {
case INC_DIRECTION: case INC_DIRECTION:
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ".out%d (",itrack); fprintf(fp, ".out%d (",itrack);
} }
fprintf(fp, "%s", fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, IN_PORT)); x, y, itrack, IN_PORT));
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ",\n"); fprintf(fp, ",\n");
break; break;
case DEC_DIRECTION: case DEC_DIRECTION:
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ".in%d (",itrack); fprintf(fp, ".in%d (",itrack);
} }
fprintf(fp, "%s", fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, OUT_PORT)); x, y, itrack, OUT_PORT));
if (true == is_explicit_mapping) { if (true == is_explicit_mapping) {
fprintf(fp, ")"); fprintf(fp, ")");
} }
fprintf(fp, ",\n"); fprintf(fp, ",\n");
break; break;
default: default:
@ -1319,20 +1319,15 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
/* Quote Routing structures: Channels */ /* Quote Routing structures: Channels */
if (TRUE == compact_routing_hierarchy ) { if (TRUE == compact_routing_hierarchy ) {
fprintf(fp, "//TEST1\n");
dump_compact_verilog_defined_channels(fp, is_explicit_mapping); dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
} else { } else {
fprintf(fp, "//TEST2\n");
dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
} }
/* Quote Routing structures: Switch Boxes */ /* Quote Routing structures: Switch Boxes */
if (TRUE == compact_routing_hierarchy ) { if (TRUE == compact_routing_hierarchy ) {
fprintf(fp, "//TEST3\n");
dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping);
} else { } else {
fprintf(fp, "//TEST4\n");
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/ dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/
} }